基于vhdl开发的频率发生器

通信中卷积交织/解交织FPGA源程序，采用verilogHDL代码实现，包含测试程序，经过验证。(Communication in the convolutional interleaving/de interleaving FPGA source program, using verilogHDL code to achieve, including test procedures, after verification.)

本程序为24小时计时器，稳定无误差。简单好用，是Verilog HDL语言初学者的指引。-This procedure for 24-hour timer, stable error-free. Easy-to-use, is the Verilog HDL language beginners guide.

测量周期,此程序已经在EP2C板子上成功实现(mesure cycle)

用CPLD驱动数码管，实现从0000计到9999，数码管是用动态显示，程序用VERILOG完成的-CPLD drives with digital control, of from 0000 to 9999, digital control is a dynamic display, the program completed with VERILOG

VHDL_modelling_guidelines是vhdl建模开发的指导资料-VHDL modeling VHDL_modelling_guidelines is guiding the development of information

這裡提供Auto Gain Control 的詳細代碼與功能介紹(Here are details of the code and the Auto Gain Control Functions)

this program get 20 point from user and draw functions.

交通灯控制（VHDL）-Traffic Light Control (VHDL)! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! !

乘法器,实现了乘法和除法的功能,能够进行32位的运算-Multiplier to achieve the functions of multiplication and division to carry out 32-bit computing

Routine for I2C in VHDL