基于vhdl开发的频率发生器

AUDIO音频模块AN831的录音及播放FPGA代码，测试通过(AUDIO audio module AN831 recording and playback of FPGA code, the test passed)

vhdl语言描述分频器，实现2、4、8、16……分频，经过实践-description language VHDL divider, 2,4,8,16 ... ... realize frequency, through the practice of

用VHDL语言将二进制数据转换成十进制数据，并将十进制的每一个位分离出来单独存放。使用状态机实现，程序简单，仿真效果很理想，占用可编程器件的资源较少。-VHDL language with the binary data into decimal data and decimal places separated from each store individually. Realize the use of state machine, the program is simple, simulation results are satisfactory, occupation of programmable devices have fewer resources.

在这里设计的是时分复用系统，就是要将三路8比特数据复用到同一信道上进行传输(Here is the design of time division multiplexing system, is to take the road three 8 bit data multiplexed onto the same channel for transmission)

世界时钟，最简单的vhdl的fpga设计，是vhdl语言的入门级，jigon供参考娱乐

this is the source code we have been working on for our project using altera de2 board. the code can be run but some of it miss the end game module, while some doesn t have the complete vga code

学习ISE的好资料，想要使用XILINX芯片进行开发必看(ISE learning good information, want to use a must-see XILINX chip development)

基于对ROM的编写，在quartusII上实现九九乘法器的实现，在试验箱的四个数码管上分别显示乘数，被乘数，积

VHDL实现快速傅立叶变换 -VHDL implementation VHDL implementation of Fast Fourier Transform Fast Fourier Transform

串口通信通用模块，FPGA Verilog语言 ise，vivado环境(uart,FPGA Verilog, ise,vivado)