1路视频光端机的发射端，VHDL源码，使用全FPGA芯片的硬件，内建成帧、时钟、SERDES...

说明：  ds18b20的Verilog程序，经测试验证可以使用。注意此版本为DALLS DS18B20而不是DS1820,注意加5K上拉电阻。(ds18b20 the Verilog process can be used to verify by testing. Note that this version rather than DALLS DS18B20 for DS1820, the attention of Canadian 5K pull-up resistor.)

用Actel公司的Fusion系列FPGA开发的LCD实验程序-Fusion with Actel s FPGA development series LCD Experimental procedures

使用VHDL实现锁相环,是个学习VHDL的好例子,与众分享-PLL using VHDL, VHDL is learning a good example, sharing with the public

hdmi 视频编解码输入输出模块，verilog实现(hdmi encoder and decoder in verilog.)

VHDL_count 从 0000 到 9999 7 段 LED 显示器 （đếm 慈 0000 đến 9999 hiển 施耐 4 领导 7 đoạn）

资源描述该乘法器可用于过滤器，算术运算和；

基于PCF8591数模转换和DDS技术的信号发生器系统设计(Design of Signal Generator System Based on PCF8591 Digital-to-Analog Conversion and DDS Technology)

GPS信号结构,C/A码产生方式及其测距码研究(GPS signal structure and ranging code research)

说明：  基于FPGA的OFDM同步，包含时钟模块、ROM读取模块、峰值检测模块、帧同步模块(OFDM synchronization based on FPGA includes clock module, Rom reading module, peak detection module and frame synchronization module)

dp_xiliux 的 CPLD Verilog设计实验,流水灯演示.代码测试通过. -dp_xiliux the CPLD Verilog design experiments, water lamp demonstration. code test.