dp_xiliux 的 CPLD Verilog设计实验,流水灯演示.代码测试通过.

代码使用应用于 FPGA的VHDL代码，主要是告诉大家时序逻辑和组合逻辑的应用场合和区别，希望能够对大家有所帮助

Multiplication in Verilog code

QP编程创始人所著的介绍QP编程思想的书，中文版。QP是用于嵌入式中状态机编程的开源软件。(QP programming book written by the founder of the introduction of QP programming ideas, and Chinese version. QP is open source software for embedded state machine programming.)

verilog 代码实现串并转换，有延迟(Verilog code and string conversion, delay)

如果需要用verilog设计一项比较简单的功能，那么这个浅显易懂的程序能让你很快明白点阵的设计方法，尤其是对那些初学者(If you need to use a relatively simple verilog design features, then this easy to understand design of the program allows you to quickly understand the lattice method, especially for those who are beginners)

超前进位加法器得VHDL实现小点资料代码(CLA was a small point of information VHDL code)

用VHDL语言实现的蜂鸣器发声程序，当按下不同按键时，发出不同频率的声音(Function:when different buttens are pressed, beep will play sound with different frequency. laguage:VHDL)

Verilog实现高速AD7606数据采样，8通道，采样频率可调，支持串口数据发送，亲测可用。(Verilog AD7606 high-speed data sampling, 8-channel, the sampling frequency is adjustable, support for serial data transmission, pro-test is available.)

飞思卡尔智能车芯片模块程序 MC9S12XS128 测试通过(freescale smart car for MC9S12XS128)

用VHDL语言编写，在MAXPLUS2下调试通过-VHDL language, debug through MAXPLUS2