登录
首页 » VHDL » This code for countor . it is design in verilog HDL.

This code for countor . it is design in verilog HDL.

于 2022-07-27 发布 文件大小:1.28 kB
0 139
下载积分: 2 下载次数: 1

代码说明:

This code for countor . it is design in verilog HDL.

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • mig_7series_v1_9
    DDR3控制器源码,针对XilinxFPGA的DDR3控制器的源码,已经验证通过。(DDR3 Controller,complete DDR3 controll,have pass verificaion.)
    2016-08-16 09:27:43下载
    积分:1
  • c_fir_ppt
    C语言写得FIR滤波器代码,简单实用,是学习滤波器设计的好材料,附带PPT滤波器设计说明(C language written FIR filter code, simple and practical, is a good learning materials of filter design, with PPT filter design )
    2020-07-04 03:00:02下载
    积分:1
  • 基于FPGA的相位测量原理图,通过对正弦信号过零比较进入FPGA,测量相位差。可用于测量导纳等应用中。...
    基于FPGA的相位测量原理图,通过对正弦信号过零比较进入FPGA,测量相位差。可用于测量导纳等应用中。
    2022-02-28 15:01:07下载
    积分:1
  • pid_controler_latest.tar
    PID控制器的verilog实现,做闭环控制器的人可以参考(PID controller verilog implementation of closed-loop controller may make reference to)
    2010-10-23 17:09:15下载
    积分:1
  • Xilinx_2018_Licenses_Downloadly.ir
    说明:  Xilinx Licenses 2018
    2020-06-25 08:20:01下载
    积分:1
  • DDR (double rate) SDRAM controller reference design Verilog code, can be directl...
    DDR(双速率)SDRAM控制器参考设计verilog代码,可以直接用的,很好的-DDR (double rate) SDRAM controller reference design Verilog code, can be directly used, very good
    2022-11-05 09:15:03下载
    积分:1
  • PerryVHDL
    VHDL Bible. It is a must read for any front end vlsi designer.
    2009-03-07 13:17:14下载
    积分:1
  • PC9054_1124
    基于FPGA的PCI9054 LOCALBUS总线接口(PCI9054 interface program based on FPGA)
    2015-04-07 09:44:02下载
    积分:1
  • sos_module
    用FPGA实现sos摩尔密码,即输出电平信号短长短。就是有次序的控制输出莫斯密码的“点”,“画”和“间隔”。而 control_module.v 是一个简单的定时触发器,每一段时间都会使能sos_module.v。(Realized by FPGA sos mole password, the output signal level of short duration. There is a sequence of output control points Moss password, painting and intervals. And control_module.v is a simple timer triggers, each period of time will enable sos_module.v.)
    2016-09-20 16:26:29下载
    积分:1
  • 8_1
    一个具有置位、复位、左移和右移功能的八位移位寄存器/“01011010”序列检测器。移位寄存器电路端口为:异步清零输入端口rst,输入时钟clk,置数判断输入端口load,移位类型判断输入端口m,数据输入端口data[7:0],输出端口q[7:0]。序列检测器电路端口为:异步清零输入端口rst,输入时钟clk,串行数据输入端口d,输出标志端口s。(A eight bit shift register / 01011010 sequence detector with set, reset, left shift, and right shift function. Shift register circuit port is: Asynchronous Clear input port rst, input clock CLK, set the number to determine the input port load, shift type to determine the input port m, data input port data[7:0], output port q[7:0]. The sequence detector circuit port is: Asynchronous Clear input port rst, input clock CLK, serial data input port D, output flag port s.)
    2020-12-17 08:29:12下载
    积分:1
  • 696516资源总数
  • 106914会员总数
  • 0今日下载