DE2 will connect to the LCD layout for Terasic off technology companies attached...

说明：  ZYNQ中 PS 端 CAN接口的基本使用方法，并通过 CAN接口实现与 PC 端 CA N调试软件之间的数据接收和发送(The basic use method of PS end can interface in zynq, and the data receiving and sending with PC end can debugging software through can interface)

三八译码器，四位加法器，EDA实验，用verilog编写(EDA experiment with verilog language)

详细的说明了FPGA设计的整个流程 FPGA设计全流程Modelsim>>Synplify.Pro>>ISE-Detailed description of the FPGA design flow of the entire FPGA design flow full Modelsim> > Synplify.Pro> > ISE

Altera Sdram IP 源码，VHDL写的-Altera Sdram IP source code, VHDL written

以嵌入式CPU和FPGA为基础的嵌入式系统架构-Embedded CPU and FPGA-based embedded system architecture

温度传感器实验，将温控芯片的温度信号通过fpga用数码管显示(temperature display)

说明：  彩条产生程序。。。。720p需添加74.25M时钟(colorbar generation. need 74.25mhz clock if 720p gen)

ethernet mac core.this is the etherenet udp application

用VHDL语言实现一个能显示时、分、秒的时钟：可分别进行时和分的手动校正；12小时、24小时计时制可选，12小时制时有上下午指示；当计时到预定时间（此时间可手动设置）时，扬声器发出闹铃信号，闹铃时间为10秒，可提前终止闹铃。-VHDL language used to achieve a display hours, minutes and seconds of the clock: when can be manually corrected and points 12 hours, optional 24-hour time system, 12-hour on the afternoon of instructions from time to time when the time to the scheduled time (This time can be manually set), the speaker sent alarm signals, alarm time was 10 seconds, the alarm can be terminated prematurely.

system gen & accel dsp 培训资料-system gen & accel dsp