四位数字乘法器，在quartus8.0下仿真时序图

AVS运动补偿电路的VLSI设计与实现 提出了一种基于AVS标准的高效的运动补偿电路硬件结构，该设计采用了8 X 8块级流 水线操作，运动矢量归一化处理和插值滤波器组保证了流水线的高效运行以及硬件资源的最优 利用。采用Verilog语言完成了VLSI设计，并通过EDA软件给出仿真和综合结果。-AVS motion compensation circuit of VLSI Design and Implementation of a standard based on the AVS motion compensation circuit efficient hardware structure, the design used 8 X 8 block-level pipelining, the normalized motion vector processing and interpolation filter bank guarantee efficient operation of the pipeline, as well as the optimal use of hardware resources. Using Verilog language completed VLSI design and EDA software through simulation and synthesis results.

用Vivado IPI搭建的Zynq-7000 PS到PL通信过程，使用了AXI-HP接口，利用AXI-DMA IP实现直接读写DDR的过程，软件可以配置传输尺寸。(The Zynq-7000 PS to PL communication process is built by Vivado IPI. AXI-HP interface is used, and AXI-DMA IP is used to read and write DDR directly. The software can configure the transmission size.)

8051IP 核源代码（VHDL）.RAR-8051IP nuclear source code (VHDL). RAR

用VHDL语言编写，在MAXPLUS2下调试通过-VHDL language, debug through MAXPLUS2

用vhdl语言编写的数字逻辑alu设计，实现包括逻辑运算乘法、加法和移位的运算功能，加入流水线处理，适用于初学硬件语言的同学们

说明：  APPCM算法和AD/DA芯片驱动在CPLD中的实现，已在实际硬件中测试OK，quartus2环境(APPCM algorithm and AD/DA chip in the drive to achieve in the CPLD has been tested in actual hardware OK, quartus2 environment)

基于fpga的交织编码器设计，主要讲叙如何在fpga上实现交织编码器。-something about turbo。

控制ADV212 压缩的源代码 使用xilinx edk开发环境(adv 212 controller, using xilinx edk)

VHDL implementation of RC6 encryption algorithm Test file represent applying all zero input and all zero key note that result is correct but bytes positions are swapped

同步与异步FIFO的verilog实现，包括源代码，testbench，测试以及综合通过，还有相关参考资料(Synchronous and asynchronous FIFO verilog achieve, including source code, testbench, test and integrated through, as well as related references)