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基于Verilog代码简单
simple code based on verilog
shifter , cla ,clg
- 2023-09-01 00:50:02下载
- 积分:1
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32_lvds_test
Xilinx 公司Spartan-6系列FPGA实现LVDS,带Modelsim仿真文件,已综合。(Xilinx Spartan-6 Series FPGA implements LVDS with Modelsim simulation file, which has been synthesized.)
- 2020-11-30 20:59:27下载
- 积分:1
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四通道DDS信号发生器
四通道DDS信号发生器,很好用的代码,大家一起分享(Four-channel DDS signal generator)
- 2021-03-08 14:49:28下载
- 积分:1
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gmii_tx_mac
实现千兆以太网数据发送,通过GMII接口向PHY写数据,控制PHY发送数据。(Implementation of Gigabit Ethernet data transmission, write data to the PHY through the GMII interface, control PHY data.)
- 2013-08-08 15:24:43下载
- 积分:1
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Altera Sdram IP 源码,VHDL写的
Altera Sdram IP 源码,VHDL写的-Altera Sdram IP source code, VHDL written
- 2022-04-21 21:08:22下载
- 积分:1
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lesson38_lcd1602_clander
基于Verilog语言编写的LCD1602显示的日历程序,类似时钟功能值得参考。(LCD1602 shows calendar program based on Verilog language, similar clock function is worth reference.)
- 2019-05-26 09:29:18下载
- 积分:1
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Flash-Memory-RAM
周立功Fusion StartKit,fpga开发板的实验例程,Flash Memory初始化RAM实验(ZLG Fusion StartKit, fpga development board test routines Flash Memory Initialize RAM experiments)
- 2013-03-07 20:36:48下载
- 积分:1
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JTAG
边界扫描技术相关资料,含各个模块的介绍。很有参考价值。(JTAG TAG CONTROLLER)
- 2016-02-24 19:10:03下载
- 积分:1
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可编程ASCII
说明: 写出13个简单的Verilog demon,适合初学者观摩学习。配合实验报告,食用更佳。(Write 13 simple Verilog demon, suitable for beginners to observe and learn. With the experimental report, it is better to eat.)
- 2020-12-28 18:59:02下载
- 积分:1
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本人编写的定点除法器,开发软件为XILINX的ISE6.2,通过PAR仿真.
本人编写的定点除法器,开发软件为XILINX的ISE6.2,通过PAR仿真.-I prepared for the sentinel division, the development of software for the ISE6.2 Xilinx, PAR through simulation.
- 2022-09-14 19:00:03下载
- 积分:1