Verilog版的C51核(DW8051)

verilog hdl教程135例:verilog hdl语言类似于C语言，便于学习。本文档带有源代码，9-10章-Verilog HDL 135 cases Guide : Verilog HDL language similar to the C language, to facilitate learning. This document with the source code, 9-10

实现任意整数倍的信号分频，可调，不存在毛刺，波形完整，可运于信号的分析与检测(Arbitrary integer multiple of the signal frequency, adjustable, there is no glitch, waveform integrity, and can transport the analysis and the detection signal)

Synopsys 8051 IP core documentation.

fpga实现ＣＡＮ总线控制器源码,每个项目都有说明文件，介绍使用方法。(fpga CAN Bus Controller source, each with explanatory documents on the use of methods.)

用Verilog HDL语言进行HDB3编码，并通过Quartus Ⅱ仿真验证(With the Verilog HDL language HDB3 coding, and simulation by Quartus Ⅱ)

说明：  Verilog 黄金参考指南是 Verilog 硬件描述语言及其语法 语义 合并以及将它应用到硬件设计的一个简明的快速参考指南。(Verilog Golden Reference Guide is a concise and fast reference guide for Verilog Hardware Description Language and its syntax and semantics merging and its application to hardware design.)

verilog HDL语言，对于超大规模集成电路开发学习非常有好处-verilog HDL language, for ultra-large-scale integrated circuits are very beneficial to the development of learning

vivado lwip 应用文档 基于zynq 7020(vivado lwip example text of zynq)

说明：  在FPGA上实现CAN总线SPI接口通信，使用Verilog语言(Realize SPI interface communication of CAN bus on FPGA, using Verilog language)

this project is based on half adder ,full adder,half subtractor and full subtractor using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural techniques are used. - this project is based on half adder ,full adder,half subtractor and full subtractor using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural techniques are used.