Verilog版的C51核(DW8051)

vga显示代码,里面有ise工程文件,是直接调过去的,大家下载下来吧-vga display code, which has ise project file is transferred directly past, everyone download it

sequenceur,该模块的主要功能是，控制器，在基本的risc架构中，实现各个模块的控制-sequenceur，control

用verilog实现dsp与Fpga接口的同步设计，其功能包括读写操作及四个功能模块，采用两个fifo实现不同时钟域的地址与数据的转换，在quartus ii11.0环境下运行，运行此程序之前需运行将调用fifo。(Dsp using verilog achieve synchronization with Fpga interface design, its features include read and write operations and four functional modules, using two different clock domains to achieve fifo address and data conversion in quartus ii11.0 environment to run, run this program required before running calls fifo.)

VHDL开发环境，四人抢答器，实现了四个人能同时抢答的功能。-VHDL development environment Answer four, and the realization of the four functions at the same time Answer.

DDR SDRAM控制器verilog代码及中文说明文档,对DDR开发很有用的哈。-Verilog source code for DDR SDRAM controler design,including guide book in chinese.

一个sram的源码程序，它是256kbx16bit的sram-An SRAM of the source program, it is the SRAM 256kbx16bit

基于FPGA的JPEG图像压缩芯片设计 -FPGA-based JPEG image compression chip design

国外的VHDL应用例子，大家可一好好参考一下！-abroad VHDL Application examples, we can make reference to a properly!

这是我从网上找到的用vhdl语言写的sdram控制器的代码。我的邮箱：wleechina@163.com-This is what I found online vhdl language used to write the sdram controller code. My mail : wleechina@163.com

VHDL写时钟，分频模块什么，实现计时。定点报时，定点闹钟，显示年月日。(verilog HDL)