Verilog版的C51核(DW8051)

Watch Dog Counter reset the output when the given timing meets.

实现qpsk解码，适合新手学习，代码简单，好用(mplementation of QPSK decoding)

小波包分解，重构轴承振动信号，Hilbert包络，FFT进行频谱分析，以获得轴承故障频率。(Wavelet packet decomposition, reconstruction of bearing vibration signal, Hilbert envelope, FFT spectrum analysis to obtain the bearing fault frequencies.)

浙江大学体系结构实验代码 实现流水线的forwarding(Architecture, Zhejiang University Experimental code pipeline forwarding)

四位静态数码管控制器，含详细的中文注释，ＶＥＲＩＬＯＴ源码．-4 static digital tube controller, with detailed notes in Chinese, VERILOT source.

bch编解码的完整版，本人已经做过fpga实现，就是按照该程序为原型，绝对可运行(bch decoding the full version, I have done fpga implementation is in accordance with the procedure for the prototype, can certainly run)

---------------------------------------------------------------------------

用verilog编写的科斯塔斯环，希望有帮助(Costas loop written in verilog helpful)

Opencore的IP Core，有实际合成过，可以用，大家参考-Opencore of the IP Core, there is a practical synthesis that we could use, we refer to see

用来检查FPGA通过PHY发送数据时是否有掉帧的现象(FPGA is used to check whether the PHY sends the data out of the frame with the phenomenon of)