MAX2 EPLD 的测试程序, VHDL语言编写.

10G高速以太网mac VERILOG源码 可仿真可实现(10G high speed Ethernet MAC verilog code can be used for synthesis or inplementation)

说明：  完成对cdcm6208的时钟芯片的配置，输出高频时钟(cdcm6208 cofigure using SPI interface)

ALTERA的FPGA的IP核的源代码,为使用ALTERA的FPGA的相关设计提供参考.-Altera FPGA IP core of the source code for the use of Altera FPGA design to provide the relevant information.

代码是一个复数乘法器，两个复数相乘，只用到了2个实数相乘，运算量少(Code is a complex multiplier, two complex multiplication, uses only real number multiplied by 2, operations less)

基于sopc技术的数字均衡器带通滤波器及12864液晶显示-Sopc technology-based digital equalizer band-pass filter and liquid crystal display 12864

图形图像H264插值算法，应用于图像视频处理(H264 graphic image interpolation algorithm is applied to image video processing)

控制ADV212 压缩的源代码 使用xilinx edk开发环境(adv 212 controller, using xilinx edk)

SPI接口VHDL代码,内有说明,很详细.-SPI interface VHDL code, which has made it clear that, in great detail.

? 熟悉IIC协议总线协议，采用IIC总线对图像采集传感器寄存器进行配置，并转换为RGB565格式。 ? 利用异步FIFO完成从摄像头输出端到SDRAM 和SDRAM 到VGA 接口各跨时钟域信号的传输和处理。 ? 利用 SDRAM 接口模块的设计，实现了刷新、读写等操作；为提高SDRAM 的读写带宽，均采用突发连续读写数据方式；并采用乒乓操作实现 CMOS 摄像头与VGA的帧率匹配。 ? 利用双线性插值方法实现对图像640×480到1024×768的放大操作。 ? 完成VGA显示接口设计。(Familiar with IIC protocol bus protocol, IIC bus is used to configure the register of image acquisition sensor and convert it into RGB565 format. Asynchronous FIFO is used to transmit and process signals across clock domain from camera output to SDRAM and SDRAM to VGA interface. With the design of SDRAM interface module, refresh, read and write operations are realized. In order to improve the read and write bandwidth of SDRAM, burst continuous read and write data mode is adopted, and table tennis operation is used to achieve frame rate matching between CMOS camera and VGA. The bilinear interpolation method is used to enlarge the image from 640*480 to 1024*768. Complete the VGA display interface design.)

利用FPGA控制VGA显示器显示字符汉字的程序，里面有注释。(VGA display with FPGA control procedures Kanji characters, there are comments.)