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add_noisem
把指定的噪声叠加到信号上去.有标准噪声库NOISEX-92,其中带有白噪声、办公室噪声、工厂噪声、汽车噪声、坦克噪声等等,在信号处理中往往需要把库中的噪声叠加到信号中去,而噪声的采样频率与纯信号的采样频率往往不一致,需要采样频率的校准。
(The specified noise superimposed to the signal up. Standard noise library NOISEX-92, with white noise, office noise, factory noise, car noise, tank noise in the signal processing often requires noise to be superimposed in the library The signal to noise of the sampling frequency and pure signal sampling frequency is often inconsistent sampling frequency of calibration.)
- 2012-08-10 14:18:33下载
- 积分:1
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Noc
credit base network on chip(network on chip (noc))
- 2020-06-19 11:40:02下载
- 积分:1
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基本的usb驱动程序的编程方法,值得一看.
基本的usb驱动程序的编程方法,值得一看.-Basic programing method for USB driver, worth reading
- 2023-03-19 01:40:04下载
- 积分:1
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Study the performance of state machine. Rar inspect the performance of state mac...
状态机的性能考察.rar
状态机的性能考察.rar-Study the performance of state machine. Rar inspect the performance of state machine. Rar
- 2023-04-13 19:15:04下载
- 积分:1
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laplace
说明: Laplace可以应用于图像的锐化,根据其原理,对于Laplace后的图像同样可以进行边缘检测。(Laplace can be applied to image sharpening. According to its principle, edge detection can also be performed for images after Laplace.)
- 2020-07-15 18:28:50下载
- 积分:1
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juanji
说明: 采用vhdl语言编写的卷积编码(2.1.7),通过调试可直接下载使用(Convolution using vhdl language code (2.1.7) can be directly downloaded through the use of debugging)
- 2010-03-31 17:55:07下载
- 积分:1
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1553B的编解码程序是有用的给大家分享分享
1553B的编解码程序很好用给大家分享 -the series 1553B decoder procedure is useful for everyone to share share
- 2022-07-28 09:59:52下载
- 积分:1
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medianfilter
图像滤波中的中值滤波,有效滤除椒盐噪声,使用verilog语言编写(Image filtering in the median filter, effectively filter out salt and pepper noise, using verilog language)
- 2011-10-13 17:08:48下载
- 积分:1
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descripe by the VHDL to drive the LCD cm12864,based on the FSM convertor,achieve...
cm12864液晶显示器的vhdl驱动代码,基于状态机的转换,实现显示功能。-descripe by the VHDL to drive the LCD cm12864,based on the FSM convertor,achieve the display function.
- 2022-12-01 22:05:03下载
- 积分:1
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用VHDL写的运动计时表程序,用Modelsim仿真已经通过,帖出来与大家分享。...
用VHDL写的运动计时表程序,用Modelsim仿真已经通过,帖出来与大家分享。-write VHDL campaign time table program, Modelsim simulation has been passed, Tie up share with you.
- 2022-01-26 05:57:13下载
- 积分:1