a good use of the Verilog Programming cpu procedures, we must make good use of.

vhdl的源文件调试 ！！！！！！！！ flv视频-VHDL source file debugging! ! ! ! ! ! ! ! flv video

EAB_VHDL

verilog，4、5分频器，5分频器占空比3：2-Verilog, 4,5 dividers, five dividers ratio of 3:2

交通灯控制器，verilog，可控制两个方向各四盏灯的亮灭，并具有时间显示(traffic light controllor，by verilog)

程序在报告中，要　用QuartusII运行，注意从word到运行环境中，可能有个别符号不兼容，重新在运行环境中输入那些符号就可以了-procedures in the report, with QuartusII operations, the attention to word from the operating environment, Some individual symbols are not compatible, the operating environment to re-enter those symbols on the

mc8051代码，里面功能齐全，调试方便(mc8051 code, inside a full-featured, easy debugging)

用FPGA 是先键盘的程序，is good for you -FPGA is the first keyboard to use the procedure, is good for you

说明：  FPGA PLL 分析，包括时序分析等等。。。。。。。。。(FPGA PLL Analysis)

每次开机都将次数加1 并存储到EEPROM。这样就能直观的看到机器的使用次数 用P1口 LED做为显示，次数大于256是将溢出，按复位模拟开机 或者直接通过开关开机(Each boot will add a number of times and stored to the EEPROM. So you can visually see the frequency of use of the machine as with P1 port LED display, the number is greater than 256 will overflow, analog power or press the reset switch power directly through)

代码文件夹： ARVI_FSM.v为顶层文件，用于模拟时用。 dataHex.dat 为模拟输入文件（只有10行，象征的意思。实际我们模拟时，dataHex.dat文件足有1个多GB） dataFormat.dat为输入文件对应的带格式的文件 使用modelsim模拟时，将dataHex.dat名字改为CPUContext.txt 结果: result.txt (Code folder: ARVI_FSM.v for top-level documents used for the simulation. dataHex.dat for analog input files (only 10 line, the meaning of the symbol. actual simulation we, dataHex.dat documents have more than one full GB) dataFormat.dat for the input file the corresponding file with modelsim simulation used to dataHex.dat name to CPUContext.txt results: result.txt)