uart串行口,用Verilog编写的.供大家参考

AD conversion using LTC1298

build a music player with nios 2

cadence verilog lanaguage and simulation course

基于BCD码的十进制ALU设计，可实现加减乘除的功能(BCD to decimal ALU based design can achieve the arithmetic function)

VHDL code for MC68000

Spartan 3e - Active Power Meter-Spartan 3e- Active Power Meter

使用并行结构对32位数据进行前导零检测，使用Verilog编程(Use parallel structure to the 32-bit data, leading zero detection, using Verilog Programming)

在Qaurtus环境下用Verilog输入实现64QAM信号的发生，用MATLAB协助验证，观察了PN序列对应的星座图。(Simulating generation of 64QAM RF Signal in Quartus II IDE,identified with MATLAB,constellation gram displayed.)

FPGA控制AD7321的模块，是本人亲自试验过的。有Verilog源码，和简单文档(Fpga control module of ad 7321, is I personally tested. Verilog source code, and simple documentation)

OPSK调制解调。代码思路很清晰，也很干净(Modulation demodulation OPSK. The code ideas very clear, and very clean)