uart串行口,用Verilog编写的.供大家参考

欢迎大家使用该程序，是在FPGA下使用开发的。请大家使用。-Welcome to use the program is to use FPGA development. Please use the.

DDS VHDL include everything of dds AD9914

一个verilog语言描写的同步fifo,包括:Fifo using declared registers for storage和Fifo using (model of) standard memory chip for storage.两种方式,包含testbench-Verilog language describes a synchronous fifo, including: Fifo using declared registers for storage and Fifo using (model of) standard memory chip for storage. In two ways, including Testbench

数字频率计VHDL程序与仿真 文件名：plj.vhd。 --功能：频率计。具有4位显示，能自动根据7位十进制计数的结果，自动选择有效数据的 --高4位进行动态显示。小数点表示是千位，即KHz。 -Digital Cymometer VHDL procedures and simulation of the file name: plj.vhd.- Function: frequency meter. With four shows that will automatically count seven decimal results, automatic selection of effective data- four for the high dynamic display. Decimal point that is 1000, or KHz.

点阵汉字显示的VHDL原程序.综合实验课程的程序,完全可以用的 希望大家支持啊-Dot-matrix characters shown in the original VHDL program. Comprehensive experimental program procedures, can be used to hope you will support the ah

VHTL PROGRAMMING COURSE

实现多路可变时分复用，包括复接器，解复接，比特同步，帧同步，分频器(Implement multi-channel variable time division multiplexing, including multiplexer, demultiplexing, bit synchronization, frame synchronization, frequency divider)

使用verilog写的频率计，可切换档位(Frequency counter using verilog write switch stalls)

使用FPGA的FIFO，状态机，乒乓操作等实现了异步UART。-The use of FPGA-FIFO, state machine, ping-pong operation to achieve the asynchronous UART.

8051的Verilog-Verilog OF 8051