LFSR模块，单个模块，实现移位寄存器，生成测试用pattern

vhdl的源文件调试 ！！！！！！！！ flv视频-VHDL source file debugging! ! ! ! ! ! ! ! flv video

SDRAM控制器 带仿真模型文件 仿真通过(Simulation model file simulation through SDRAM controller)

Fully parametrizable combinatorial parallel LFSR/CRC module. Implements an unrolled LFSR next state computation. Includes full MyHDL testbench.

spartan6 里使用DDR3IP核，有教程以及源码(spartan6 with ddr3,source and tutorial)

串口通讯，与硬件联通调试过，收发程序是分开的。(Serial Communication)

cycloneIII_3c120_dev_power_demo atlera公司官方例程(cycloneIII_3c120_dev_power_demo atlera company official routines)

说明：  高清电子书4本合集-Verilog HDL数字系统设计教程4本合集(Digital circuit design Verilog HDL digital system design)

说明：  实现中采用 Verilog HDL 描述、 ModelSim 进行功能仿真、 Quartus II 进行逻辑综合和适配下载(Design of table tennis game machine)

应用vhdl语言进行加法器的设计，比较器的设计，随着vhdl语言的应用越来越广泛，其重要性也更加明确。希望对大家有所帮助。-application vhdl language adder design, compared with the design, With vhdl language widely used, the importance of which was more explicit. We want to help.

master spi的源代码（verilog），包括文档，测试程序(master spi the source code (verilog), including documentation, testing procedures)