Arbitrary odd

异步FIFO 设计源代码，内涵完整的verilog源代码和测试代码。-Source code for asyn_fifo using verilog language.

扰码器的verilog实现,参考802.11a相关标准(Scrambler in verilog implementation)

设计一个能进行时、分、秒计时的十二小时制或二十四小时制的数字钟，并具有定时与闹钟功能，能在设定的时间发出闹铃音，能非常方便地对小时、分钟和秒进行手动调节以校准时间，每逢整点，产生报时音报时。 实验平台： 1. 一台PC机； 2. MAX+PLUSII10.1。 Verilog HDL语言实现,还有完整的实验报告-The design of a can be hours, minutes, seconds time of 12 hours or 24 hours system, digital clock, and has from time to time with the alarm clock function, can be set to issue a sound alarm can be very convenient to hours, minutes and seconds for manual adjustment to calibrate the time, whenever there is the whole point, resulting in timekeeping timekeeping tone. Experimental platform: 1. A PC machine 2. MAX+ PLUSII10.1. Verilog HDL language, as well as a complete experimental report

使用ALTERA上DE2平台，使用Verilog描述，交通灯控制。-Using ALTERA on DE2 platform, use the Verilog description of the traffic light control.

xilinx CTC IPcore(encoder 和 decoder)的测试，经过AWGN信道。 -This simulation uses a AWGN module to include noise as part of the simulation. Prior to running the simulation, the UniSim models for the encoder and decoder must be generated as well as the AWGN module.

非常有用的IP核资源，里面包含了JTAG,MEMORY,PCI，SDRAM和USB1.1等内容，期望对大家有用-A very useful IP core resources, which includes the JTAG, MEMORY, PCI, SDRAM, and USB1.1 and other content, expectations for all of us

ldpc编解码程序。有testbentch。-ldpc encoding and decoding process. There testbentch.

thesis for simple virus detection processor which is developed in xilinx

学习使用HDL Bencher生成测试积累，并直接调用ModelSim进行仿真的方法.-learning HDL Bencher generate test accumulation, and called directly ModelSim simulation methods.

fpga串口收发完整程序，Verilog语言。(FPGA configuration PLL complete program, Verilog language.)