Arbitrary odd

altera的关于对数计算的IP core。-altera calculated on the logarithm of the IP core.

说明：  之前一直找不到自学编写了一个，PID案例，分享下(I have been unable to find a self-taught, compiled a PID case, share under)

该程序实现的是n位全加器，首先用与非门实现一位全家器，最后实现n位的全加器。-the program is to achieve the n-bit full adder, first using the door with non-realization of a family- and finally realize the full n-bit adder.

VHDL黄金参考手册，能让你更好的学习了解VHDL语言(VHDL gold reference manual, can make you a better learn VHDL language)

Test for VHDL just a student version

介绍了光纤光栅感温火灾探测系统的应用原 理，并重点阐述了用CPLD 设计虚拟MC14499 器件模 块，给出并解释了用Verilog HDL 语言实现的部分程 序和仿真测试结果。-Introduction of Fiber Bragg Grating temperature fire detection system principles, and focuses on the use of CPLD design virtual MC14499 device module, are given and explained using the Verilog HDL language to achieve some of the procedures and simulation test results.

这是一个很全的HDB3译码的verilog程序，用于FPGA入门所用，verilog的入门很好的程序(This is a very wide of the HDB3 decoding verilog program for entry-FPGA used, verilog entry procedures for good)

spartan6 里使用DDR3IP核，有教程以及源码(spartan6 with ddr3,source and tutorial)

这是利用VHDL编写的一个CRC32的代码，文档只有代码，具体原理请参考其他文献-This is the use of VHDL prepared a CRC32-code, the document is only a code Please refer to specific tenets of other literature

EDA技术及其应用《序列信号发生器的设计》，包括源文件。(EDA technology and its applications " sequence signal generator design, including source files.)