十六进制7Segment时钟

存储器DDR3在Xlinix平台上的设计教程和综合应用(Design course and comprehensive application of memory DDR3 on Xlinix platform)

verilog中调用门级电路的实验程序，实现了门级舰模-call Verilog gate-level circuit of the experimental procedures, to achieve a gate-level ship-mode

采用VHDL编写的七段数码管显示程序-prepared using VHDL paragraph 107 of the procedures Digital Display

三相PWM整流，实现功率双向流动,可保持直流侧电压稳定(three-phase PWM rectifier, power can bidirectional flow ，can maintain the stable DC voltage)

辛辛苦苦的作品应用于DE2 的 开发。。希望对大家有用。-hard work for Dictyophora development. . We hope that the right useful.

vc707 board getting started guide

DDS在现在运用月来越广泛，在相对带宽、频率转换时间、相位连续性、正交输出、高分辨力以及集成化等方面都远远超过了传统频率合成技术所能达到的水平，为系统提供了优于模拟信号源的性能。利用DDS技术可以很方便地实现多种信号。在FPGA上实现的DDS-DDS now to the use of more extensive relative bandwidth, frequency conversion time, phase continuity, quadrature output, high-resolution and integration, and other aspects far more than the traditional frequency synthesizer technology can achieve the level To provide a superior analog signal source performance. DDS technology can be used very easily to a variety of signal. FPGA Implementation of DDS

用硬件描述语言编程实现减法器,实现两个操作数的减法-Using hardware description language programming subtraction, and the achievement of the two operands of the subtraction

d5m的DE2驱动Verilog HDL (d5m driven on DE2 by Verilog HDL )

verilog 或门程序 初学者必备。。。。。。。。。。。。(verilog )