VHDL_COUNTING 000_255 LCD DISPLAY ( ĐẾM 000 ĐẾN 255 HIỂN THỊ LCD BẰNG NGÔN NGỮ VHDL)

基于ALINX AX7020硬件平台的USB-OTG通信程序。操作系统采用uCOS III v1.41，基本实现了双向USB2.0 块传输（Bulk Transfer）通信，zynq的PS端接收USB数据并回传至主机。经测试，主机端Window10系统采用libUSBK编程时，采用64字节的块时，传输速率可达210Mbps。zynq开发工具为Vivado2015.4，程序包中包含了全部的硬件和软件工程文档。(A USB-OTG communication project where an AX7020 platform is employed as USB device. The embeded operating system is uCOS III of version 1.41, and the FPGA toolchain is Vivado 2015.4. This project implements a full speed bidirectional USB2.0 bulk transfer. A test on Windows 10 host with libUSBK shows that the transfer speed is up to 201Mbps.)

电子设计自动化中的计数器的实现程序，基于VHDL语言完成的-Electronic design automation in the realization of counter procedures, based on the VHDL language completed

大屏幕led点阵显示的驱动时序。 使用vhdl语言描述。其中rom文件可以使用lpm_megcore自动生成。-big screen led to the dot matrix display driver timing. The use of VHDL description language. Rom which documents can be automatically generated using lpm_megcore.

Design of a GF(64)-LDPC Decoder Based on the EMS Algorithm

基于fpga的数字电压表的设计，包括ad转换，bcd码转换，分频，3选1模块，小数点生成模块，显示模块组成。(Based on the FPGA digital voltage meter design, including AD conversion, BCD code conversion, frequency,3 choose1module, a decimal point generating module, display module. )

利用fpga实现gmsk的调制并仿真，全部代码(Fpga implements gmsk)

说明：  文档科斯塔斯环路滤波器。。。。。般若撒根本(wendangsafwrfgvearbeabf)

本程序显示在 BCD display 数从 0 到 9999.This 程序进行了智能 2 FPGA 板。

利用Verilog语言中的函数调用实现阶乘运算的功能(Function calls use Verilog language implementation of the factorial function computing)

完成cmos摄像头对图像的捕捉，然后进行拼接通过USB进行传输。(complete picture capture)