VHDL_COUNTING 000_255 LCD DISPLAY ( ĐẾM 000 ĐẾN 255 HIỂN THỊ LCD BẰNG NGÔN NGỮ VHDL)

SEG7数码管显示示例程序，适用于ALTERA的CPLD(SEG7 digital display sample program of ALTERA CPLD)

Blessing_3_v3_9_6稳定盈利set，仅限AUDNZD货币对，周期M1。 使用本压缩包内的SET，LAF默认是15，根据历史测试来看具有较大的风险，需要手动规避数据。 合理设置为LAF=8，请自行设置和调试，找到自己合适的风险值。 (Blessing_3_v3_9_6 stable profit set, only AUDNZD currency pairs, cycle M1. Use this package in the SET, the default is 15 fans, according to the angles of history test has great risk, need to avoid data manually. Reasonable set to fans = 8, please make your own setting and debugging, find their proper risk value.)

说明：  bt1120设计方案，描述了具体的方案设计以及整体的架构设计(Bt1120 design scheme, describes the specific scheme design and the overall architectural design)

RS（255，223）编码器，已实际运用到产品中(RS (255,223) encoder has actually applied to products)

verilog for full_adder

is61lv25616简单的verilog程序，完成sram读写 主要是基于FPGA(EP2C8Q208I8)下的SRAM驱动(1lv25616 simple verilog program, complete sram read and w1lv25616 simple verilog program, complete sram read)

Cypress USB 的主从FPGA 控制实现代码(USB controller)

由Verilog编写在FPGA实现sobel算法应用于图像边缘检测，工程文件可在quartus13.1以上版本打开；工程使用到ram、fifo、pll三种ip核，design文件夹下包含ram、fifo、vga控制以及串口收发和sobel算法模块，sim和doc文件夹下分别包含modelsim的仿真模块和仿真结果；测试时将200*200分辨率的图片用matlab文件夹下的matlab脚本压缩、二值化，再将生成文件中数据用串口发给FPGA，边缘检测结果会通过VGA输出。(Written by Verilog in the FPGA implementation sobel algorithm applied to the edge detection of the image, the project file can be opened in the quartus13.1 or later project use ram, fifo, pll three ip kernel, design folder contains ram, fifo, vga control and Serial port transceiver and sobel algorithm module, sim and doc folder, respectively, include modelsim simulation module and simulation results test will be 200* 200 resolution picture matlab folder under the matlab script compression, binarization, and then generated Data in the file with the serial port to the FPGA, edge detection results will be output through the VGA.)

说明：  使用FPGA实现中值滤波算法，能够使数据直接使用该系统对数据进行中值滤波。(FPGA is used to realize the median filtering algorithm, which can make the data directly use the system for median filtering.)

eda技术与vhdl课件,很经典的学习课件-VHDL EDA technology and courseware, it is a classic learning courseware