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VHDL-development
VHDL入门级好教材《VHDL开发精解与实例剖析》(VHDL development solution with fine examples of analysis)
- 2015-03-11 10:57:53下载
- 积分:1
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ZEDBOARD
说明: ZEDBOARD的管脚分配图和约束文件,包括PCB图和xdc文件(Pin assignment of ZEDBOARD)
- 2021-03-23 21:19:15下载
- 积分:1
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VGA FPGA时序仿真,仿真的PS / 2键盘接口VHDL源C.
用FPGA模拟VGA时序、模拟PS/2总线的键盘接口VHDL源代码,基于Xilinx spartan3-VGA FPGA timing simulation, simulation PS/2 keyboard interface bus VHDL source code, Based on Xilinx spartan3
- 2023-01-19 01:15:04下载
- 积分:1
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12
说明: 用FPGA进行等精度频率和相位差测量的程序,本程序是在EPEC6Q240C8下的程序(Carried out with the FPGA such as the frequency and phase measurement precision of the procedure, this procedure was the procedure under the EPEC6Q240C8)
- 2010-03-03 17:42:11下载
- 积分:1
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source
FPGA与SDRAM 的 VHDL 接口设计(the interface of FPGA and SDRAM)
- 2012-03-28 22:17:19下载
- 积分:1
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nor_flash_core
Verilog实现的NOR FLASH控制器,基于M25P128开发,功能完整,简洁易懂,自用无问题。(Verilog implementations NOR FLASH controller, based M25P128 development, full-featured, easy to read, for personal use, no problem.)
- 2021-03-09 14:09:27下载
- 积分:1
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dds在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过...
dds在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-dds dspbuilder under the VHDL source code and test incentives document matl ab model, the simulation under through modelsim
- 2022-06-20 23:49:32下载
- 积分:1
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StopWatch
This is a simple verilog code for stopwatch undre xlinx ISE webpack based for NEXYS3 board.
- 2013-10-04 00:53:49下载
- 积分:1
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newViterbi217
基于IEEE802.11n标准,采用verilog语言设计的(2,1,7)卷积码viterbi译码器,支持1/2,2/3,3/4,5/6四种码率的译码,以测试无误(IEEE802.11n standard Verilog language design (2,1,7) convolutional code viterbi decoder support 1/2, 2/3, 3/4, 5/6 four bit rate decoding to test and correct)
- 2020-06-29 08:40:01下载
- 积分:1
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cyc2_cii5v1
这是1C6开发板上元件的具体资料。此开发板有掉电不丢失程序的功能,就是靠着几个芯片(development board components specific information. This development board is not lost restart procedures, it was relying on a few chips)
- 2007-02-15 10:22:14下载
- 积分:1