用verilog写的各种实用的分频器，很好的参考例子。

FPGA与DSP的EMIFA口接口程序.在FPGA内分配了两块双BUFFER与DSP进行通信.-FPGA and DSP EMIFA mouth interface program. The FPGA distribution within the two-SUBJECT ER and DSP communication.

Cadence的VHDL运算库包，实现求方根，平方你是不是以前不知道怎么弄．哈哈．-Cadence VHDL Operational the package, seeking to achieve root, You are not square did not know how get. Ha ha.

VHDL实现SPI功能源代码 -- The SPI bus is a 3 wire bus that in effect links a serial shift -- register between the "master" and the "slave". Typically both the -- master and slave have an 8 bit shift register so the combined -- register is 16 bits. When an SPI transfer takes place, the master and -- slave shift their shift registers 8 bits and thus exchange their 8 -- bit register values.(SPI realize the functional VHDL source code The SPI bus is a 3 wire bus that in effect links a serial shift register between the )

VHDL由简单存储器，计数器等搭建最终实现8位的cpu设计(VHDL realization 8 of cpu design)

Verilog HDL实现的I2C Slave模拟-achieve the Verilog HDL simulation I2C Slave

Image Embedded VHDL Code by using watermarking technique

fifo异步串口收发程序 FPGA程序(fifo asynchronous serial transceiver)

imp book for cmos technology

4：2优先编码设计中的VHDL来为每个输入分配优先级。在CMOS布局1复用器：还设计了4个

高精度小数除法器设计与实现。 在FPGA开发板上实现小数除法器，输入输出信号N_in [15:0], D_in[15:0]，N_in[15:0]小于D_in，即被除数小于除数，输出商Q_out[15:0]中Q[15]一定为0，Q[14:0]为商的小数部分。输入和计算结果通过VGA显示。(Precision fractional divider design and implementation. In the FPGA development board fractional divider, input and output signals N_in [15: 0], D_in [15: 0], N_in [15: 0] less than D_in, ie the dividend is less than the divisor, quotient output Q_out [15: 0] in Q [15] necessarily 0, Q [14: 0] for the business of the fractional part. Input and calculation results display by VGA.)