用verilog写的各种实用的分频器，很好的参考例子。

通过代码控制音频编/解码硬件芯片WM8731， 通过按键控制音频输出的音量(Audio codec hardware chip WM8731 is controlled by code, and audio output volume is controlled by keys.)

这是基于verilog hdl的数字时钟源代码，能够实现时分秒的计时，可以手动进行调时与调分。(This is based on the digital clock verilog hdl source code, can be achieved when every minute of the time, you can adjust the time manually adjusting points.)

上海大学 Verilog PPT 适合初学者看 推荐 -Shanghai University Verilog PPT look recommended for beginners

最终FFT 64点使用定点。

modelsim快速入门教程，附带文中范例源代码。-ModelSim Quick Start Guide, incidental text in an example of source code.

里面是VHDL的一些例子，大家可以看一下，蛮不错的，对大家提高VHDL水平很好的.-There is some examples of VHDL, we can look pretty good on the U.S. improve the level VHDL good.

FPGA编程实现串口通信，源代码全。包括仿真程序。-FPGA programming serial communications, the entire source code. Including the simulation program.

基于FPGA的任意波形信号发生器,可实现频率、幅度、相位的调节，输出方波、正弦波、锯齿波(Arbitrary waveform generator based on FPGA)

说明：  this file describes the steps in building a fifo buffer module in verilog hdl and programming them on an fpga device

FPGA 12864显示程序 VHDL程序！！(FPGA 12864 show program )