svpwm

simple code based on verilog shifter , cla ,clg , ALU , PC

PLD与8051接口的参考设计 Xilinx提供的verilog源代码-PLD 8051 interface with the Xilinx Reference Design for the Verilog source code

使用Xilinx3S400开发的钢板检测算法中心化算法，通过测试。(a vhdl-program use Xilinx3S400)

关于VHDL和verilog的数码管显示程序，写的很好，值得参考。(About VHDL and verilog digital tube display program, write well, worth considering.)

用VHDL语言写的VGA核心,是个很好很齐全的核心,有很多功能.-write VHDL VGA core, is a very good subset of the core, has a lot of functions.

通过VHDL语言进行数字信号处理的FIR操作，可以很好的实现滤波功能，有很好的作用，-Through VHDL languages digital signal processing FIR operation, can good realization filtering, have good role

本代码用verilog语言配合sopc和nios实现了串口调试的目的。软件编程用C语言描述，只是比较简单的例子，适合初学者做了解用，本人亲自在EP2C8Q上实践。(The code to use verilog language sopc and nios achieved with serial debugging purposes. Software programming using C language description, but relatively simple example for beginners to do with understanding, I personally EP2C8Q on practice.)

说明：  how to come ture a costas loop in FPGA with verilog,it is very useful on project

VHDL implementation of RC6 encryption algorithm Test file represent applying all zero input and all zero key note that result is correct but bytes positions are swapped

Xilinx user constraints file for the cpld xc9536 or xc9536xl or xc9572 or xc9572xl