svpwm

基于Verilog HDL的通信系统设计(Design of communication system based on Verilog HDL)

说明：  本实验为UART回环实例，实验程序分为顶层unrt_top、发送模块uart_tx、接收模块 uart_rx，以及时钟产生模块clk＿div。uart＿rx将收到的包解析出8位的数据，再传送给 uart_tx发出，形成回环。参考时钟频率为100MHz，波特率设定为9600bps。(This experiment is an example of UART loop. The experimental program is divided into top-level unrt_top, sending module uart_tx, receiving module uart_rx, and clock generation module clk_div. Uart_rx parses the received packet into 8 bits of data and sends it to uart_tx to send out, forming a loop. The reference clock frequency is 100 MHz and the baud rate is set to 9600 bps. stay)

该项目实现了在Altera FPGA中的乒乓球比赛。游戏控制器是建立在FPGA中。玩家使用它连接到FPGA开发板玩的游戏键盘。本场比赛显示VGA屏幕上。所有部件，如键盘，VGA屏幕是由控制装置控制。

简易电子钟的设计（verilog HDL）(Simple design of the electronic clock (verilog HDL))

说明：  基于蜂鸟E203riscv系统的DMA外设代码(DMA code based on hbird_e203 system)

un controller pi par le langage VHDL xilinx ise design 13.2

说明：  使用DE2实现DDS，步骤简单，配置管脚可自查看(Using DE2 to realize DDS, the steps are simple and the pins can be self-checked.)

完成cmos摄像头对图像的捕捉，然后进行拼接通过USB进行传输。(complete picture capture)

AMBA总线的AHB+APB源程序，供初学者学习。(Verilog for AHB and APB)

说明：  基于旋转编码器和LED灯组的强度调节系统设计(Design of Intensity Regulation System Based on Rotary Encoder and LED Lamp Set)