EPM570并串转换器

美国人写的各种类型的fpag设计指导，非常详细的介绍了从fpga的型号，结构，实现，编程，等各个方面的要点。-Written by Americans of all types of fpag design guide, very detailed introduction from the FPGA models, structure, realize, programming, and other aspects of the main points.

基于fpga和sopc的用VHDL语言编写的EDA的32位Nios CPU嵌入式系统及其DMA设计俄罗斯方块游戏机(FPGA and SOPC based on the use of VHDL language EDA 32-bit Nios CPU and the DMA design of embedded systems Tetris game)

vhdl学习基本编写程序，关于温度的读取和显示，vhdl学习基本编写程序，关于温度的读取和显示，vhdl学习基本编写程序，关于温度的读取和显示

tPad DE2-115/70开发板可用的摄像头采集、显示程序，QT10.0以上环境可用，原装代码，可以进行修改加以使用，如使用到倒车影像系统中，视频显示等。(tPad DE2-115/70 development board available cameras capture, display program, QT10.0 over the environment is available, the original code can be modified to be used, such as the use of the reversing video system, the video display.)

4*4键盘设计，能运行，是我自己编译的，是初学者的工具(4* 4 keyboard design, can run my own compilation, is a tool for beginners)

papers based on distributed arithmetic.

正弦波在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-sine wave in dspbuilder under VHDL source code and test incentives document matl ab model, the simulation under through modelsim

把指定的噪声叠加到信号上去.有标准噪声库NOISEX-92，其中带有白噪声、办公室噪声、工厂噪声、汽车噪声、坦克噪声等等，在信号处理中往往需要把库中的噪声叠加到信号中去，而噪声的采样频率与纯信号的采样频率往往不一致，需要采样频率的校准。 (The specified noise superimposed to the signal up. Standard noise library NOISEX-92, with white noise, office noise, factory noise, car noise, tank noise in the signal processing often requires noise to be superimposed in the library The signal to noise of the sampling frequency and pure signal sampling frequency is often inconsistent sampling frequency of calibration.)

说明：  1、能正确显示输入信号频率； 2、测量频率范围为1Hz ~ 999999Hz； 3、测量结果以十进制数字显示； 4、能测量幅值较小的信号频率； 5、有自动刷新输出数据的功能（如5s刷新一次）； 6、有自检模块（如产生100Hz的校准方波）；(1. It can correctly display the input signal frequency; 2. The frequency range of measurement is 1Hz ~ 99999hz; 3. The measurement results are displayed in decimal; 4. It can measure signal frequency with small amplitude; 5. It has the function of automatically refreshing the output data (e.g. once in 5S); 6. Self checking module (such as generating 100Hz calibration square wave);)

DE2 altera board vhdl design