xilinx xc9572 cpld 实现的伺服电机控制器，电机控制输出，和增量编码器读取。...

Triscend supports the use of the Model Technology ModelSim logic simulator for VHDL simulation of designs implemented in the Configurable System Logic (CSL) portion of a Triscend device.

秒表 东北大学秦皇岛分校 电子设计自动化 实验(Stopwatch Northeastern University at Qinhuangdao electronic design automation experiment)

lattice的官方8b10b代码, 1012年版本，diamond3.5编译。(lattice 8b10b encoder decoder code)

说明：  ADC Reference code!Clock 100kHz

半带滤波器，用于sigma-delta DAC中的设计(Half-band filter for sigma-delta DAC design)

一个Verilog的JTAG程序例子，包括完整的说明文档和源文件。(tap_top.v This file is part of the JTAG Test Access Port (TAP) http://www.opencores.org/projects/jtag/ Author(s): Igor Mohor (igorm@opencores.org))

vga controller vhdl, it draws 3 lines -vga controller vhdl, it draws 3 lines

VHDL电子抢答器的实现。有多个文件，主控件是用图行实现。其余各功能模块用VHDL实现-VHDL electronic Responder realized. A number of documents, the main controls are using maps the bank. The remaining modules using VHDL

VHDL，verilog串并转换源程序 Xilinx公司参考资料-VHDL, verilog Series and conversion company Xilinx reference source

4-16译码器，用VHDL编写的，可以直接下载到可编程逻辑器件中(4-16 decoder, written with VHDL, can be directly downloaded to the programmable logic device)