xilinx xc9572 cpld 实现的伺服电机控制器，电机控制输出，和增量编码器读取。...

这是篇<基于FPGA 的OFDM 宽带数据通信同步系统设计与实现>, 觉得甚是有用，大家共同学学。(This is the article <FPGA-OFDM-based broadband data communication systems design and implementation of synchronous> that even be useful, we all learn together.)

说明：  【实例简介】用Verilog实现uart串口协议，波特率可选9600、19200、38400、115200。8位数据为，1位校验位，1位停止位。 【实例截图】 【核心代码】核心代码包括TX，RX，Baud，FIFO([example introduction] UART serial port protocol is implemented with Verilog, and the baud rate can be 9600, 19200, 38400, 115200. 8-bit data, 1 bit check bit, 1 stop bit. [example screenshot] [core code] the core code includes TX, Rx, baud and FIFO)

FPGA verilog 实现任意位宽的移位相乘法，有符号小数或者有符号整数相乘。函数调用方式(FPGA verilog achieve any bit-wide shift multiplication , signed or signed decimal integer multiplication . Function call )

FPGA的专业综合工具，学习此第三方工具的经典教程-FPGA 专 业 酆 危 撸 学魏 说 叩 木坛

基于FPGA的VHDL可以产生不同的音调,象音乐一样-based FPGA VHDL can produce different tones, like the same music

vhdl very good debug release vhdl very good debug release

verilog code for apb to ahb convert

自已写的一个16X16的乘法器，速度比较慢。初学者练习练习！-own writing an audio Multiplier, speed is relatively slow. Beginners practice practice!

FPGA实现基于cordic算法的指数函数的程序(FPGA implementation of an exponential function program based on the cordic algorithm)

基于SDRAM的PCI采集,上位机为VC编写，桥芯片为PLX9054，项目已经做完，上传5个例程，已经验证通过(SDRAM, PCI-based acquisition, PC for VC preparation, bridge chip for PLX9054, the project has been done, upload 5 routines, has been verified by)