Verilog版的C51核(OC8051)

一个32位元的浮点数加法器，可将两IEEE 754格式内的值进行相加(A 32-bit floating-point adder can be both within the IEEE 754 format to add value)

6层电梯设计，采用vhdl编写，能够实验电梯功能(6-story elevator design, using vhdl prepared, able to lift function experiments)

用FPGA模拟VGA时序、模拟PS/2总线的键盘接口VHDL源代码，基于Xilinx spartan3-VGA FPGA timing simulation, simulation PS/2 keyboard interface bus VHDL source code, Based on Xilinx spartan3

说明：  基于Xilinx Spartan6系列的fpga的VGA实现(Based on Xilinx Spartan6 series fpga VGA implementation)

System Verilog decodificator. Enters a value(binary), drops hundreds, tens and units in BCD

verilog编写的流水线模块-Verilog modules prepared by the Pipeline

串行数据开发实用代码， 适合初级学习者使用 很不错(Serial data to develop a practical code for primary learners use very good)

说明：  displayport 参考设计，可以对比自己工程做验证，另有参考设计XAPP1178未找到，采用方案为DP159 + Artix7 FPGA(xilinx displayport sink design)

VERILOG HDL pid算法 带仿真验证(pid by verilog HDL)