Verilog版的C51核(OC8051)

Altera DE2 上使用 vhdl 语言设计 RS232 控制器。这是一个串口模块可用于嵌入系统。

设计了一个电子时钟，功能包括定点报时，设置闹钟，校时等(Designed an electronic clock, features include fixed-point timekeeping, setting alarms, school hours, etc.)

offset_cancellation code for matlab to hdl

16位右移位寄存器 下面描述的是一个位宽为16位的右移位寄存器，实际具有环形移位的功能，是在右移位寄存器的基础上将最低位的输出端接到最高位的输入端构成的。其功能为当时钟上升沿到达时，输入信号的最低位移位到最高位，其余各位依次向右移动一位。(16-bit right shift register The following description is a right shift register with a bit width of 16 bits. It actually has the function of circular shift. It is based on the right shift register, which connects the lowest bit output terminal to the highest bit input terminal. Its function is that when the rising edge of the clock arrives, the lowest displacement of the input signal reaches the highest position, and the rest of you move one bit to the right in turn.)

FPGA编写环境，具有仿真容易，软件内存小的特点(FPGA authoring environment, with easy simulation software features small memory)

24bitAD数据采样进行串并转换，并行输出。另包括24位DA并串转换，串行输出。(24bitAD data sampling and converted to strings, parallel output. Other notable features include 24-bit DA and string conversion, serial output.)

说明：  使用FPGA实现RGB图像转灰度图像的算法，下载入自己的电路板可直接将摄像头拍摄到的图像实时转换成灰度图像(FPGA is used to realize the algorithm of transforming RGB image into gray image. The image captured by the camera can be converted into gray image in real time by downloading it into its own circuit board)

本文首先回顾了LDPC码的发展历程和现状，介绍了LDPC码检验矩阵的构造、编 译码原理。在对编译码作了深入探讨和分析后，接着进行了RU算法编码和长码编码 的FPGA实现;根据二叉树的性质，提出了一种长码编码的ASIC优化设计的方法，节省 了大量硬件资源;论文详细阐述了CORDIC算法原理以及LDPC码译码中所采用的指 数函数和反双曲正切函数的FPGA实现:CORDIC内核及前后处理单元设计、仿真、综 合及数据分析，这对LDPC码的译码具有很重要的意义，为用数字VLSI来实现LDPC的 译码奠定了基础。同时在基于校验矩阵的环路检测定理基础上，将校验矩阵转化为转 移概率矩阵，详细分析并提出了一种基于转移概率矩阵的围长检测方法，并对其进行 了理论证明，具有很好的围长检测效果，以及状态分类判别。(Research and implementation of LDPC coding and decoding technology)

A 4 bit twisted ring counter is a sequential circuit which produces the following sequence of output values: 0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001 and then repeats. Design a circuit for a 4 bit twisted ring counter that uses four D flip flops. Draw a state transition diagram, a state table and a schematic for your circuit. Design an alternate implementation using just three flip flops and draw a state transition diagram, state table and a schematic for your circuit. If your designs are extended to implement an n bit twisted ring counter, how many flip flops are required using each of the two approaches. In what situations would you prefer the first method? In what situations would you prefer the second?

一个AD9764的基于FPGA的驱动，希望对有需要的朋友有所帮助(An AD9764 FPGA-based drive, we want to help a friend in need)