Data Encryption Standard or DES

简单的apb i2s接口，verilog代码，包括rtl实现和testbench(apb i2s interface . coded by Verilog. including rtl and testbench)

verilog 代码. 经验证成功,可以作为标准单元库,为FPGA设计者使用.-Verilog code. Certified success, as a standard cell library for the use of FPGA designers.

利用VHDL语言和模块化设计实现PCM编译码的功能，整体工程和代码全有。(PCM encode and decode by VHDL in Quartus2. )

这时manchesite编码，VERILOG语言，VHDL的找本站我发的帖子-manchesite time coding, VERILOG language, VHDL I find a site in a posting

16QAM调制解调程序画出时域波形、 正交分量、同相分量波形，眼图，散点图等(16QAM modulation and demodulation process to draw time-domain waveform, quadrature components, in-phase component waveforms, eye diagrams, scatter plots, etc.)

测试过可用的SD仿真模型，VERILOG语言(SD card simulation modle, test OK)

本代码实现了全加器的功能，可供初学者学习-This code implements a full adder functions, for beginners to learn

说明：  运用Verilog 语言进行数字积分法，将X轴和Y轴进行插补运算。(Verilog language using digital integration method, the X axis and Y axis interpolation operations.)

FPGA驱动高输入电压范围的ADS8509芯片，采样范围广，适合前端大信号处理(FPGA drive a high input voltage range ADS8509 chip, sampling a wide range, suitable for large front-end signal processing)