一个有关于UART开发的自己的一个VHDL代码

一个SDH中最基本传输模块STM-1的帧头检测器，verilog编程实现-A basic SDH transmission module STM-1 Header detector, verilog Programming

基于FPGA的电子密码锁的设计，内有Verilog HDL源码和各仿真图像-FPGA-based design of electronic locks, which have Verilog HDL source code and the simulation image

ES A PRACRICA 2 DEL LABORATORIO DE DIGITAL

ps2接口的工程实现，顶层为原理图，便于理解-ps2 interface engineering implementation, the top-level schematic diagram for easy understanding of

本程序为Verlog语言程序，采用QUARTUS6.0编写，程序实现的功能是控制AD2S80的转换和和数据总线上数据的读取-This program is Verlog language program, using QUARTUS6.0 preparation, program implementation function is to control the conversion and AD2S80 and data bus to read data

Multipleksor 3 to 1 - 3x1bit in, 1x1bit out

802.1as gptp标准包解析verilog模块。用于实现EAVB协议的重要部分。(802.1as gptp verilog module, part of EAVB procotol)

EMIF接口调试代码，使用的是Verilog语言，FPGA与DSP通信，测试成功(EMIF interface debugging code that USES the Verilog language, FPGA and DSP communication, testing success)

vhdl project at sbu uni in iran uart