Quartus senior io distribution, manual example

在Altera_PFGA上实现POWERLINK从站设计,这是目前最好的的最具爱的实现方案，具有很实用的参考价值。文章介绍了实现方案和主要思路。

VERILOG HDL pid算法 带仿真验证(pid by verilog HDL)

说明：  银行排队系统的VHDL程序实现，可以实现排队顾客自动取号，查看前面排队人数，银行服务柜台号等。(Bank queuing system VHDL program can be achieved automatically check its customers lined up to view the queue in front of the number of its banking services, such as counters.)

lacp代码，可以参照学习Lacp协议的相关状态机等知识(LACP code, can refer to the relevant state machine learning knowledge of Lacp protocol)

用状态机实现一序列检测器，即检测到串行码{1110010}后，检测器输出1，否则输出0； -State machine used to achieve one sequence detector, which detects the serial code (1110010), the detector output 1, otherwise output 0

Very good info. for RS-232 echo VHDL code .

和picoblaze完全兼容的mcu ip core-And PicoBlaze fully compatible mcu ip core

在接收信号的数字化、软化的实现中,数字下变频起着重要的作用。本文首先介绍了数字下 变频的组成结构,然后详细分析了数字下变频的工作原理,描述了在实现数字下变频时,设计方案所 采用的高效滤波器———CIC 滤波器和多相抽取滤波器的结构和原理。最后,用通过Simulink 对数字 下变频的性能进行了仿真。在仿真的基础上使用Insight 公司的FPGA 开发系统,用测试电路实测了 数字下变频的性(In the receiving digital signal, softening the realization, the digital down-conversion plays an important role. This article first introduced the digital down conversion of the composition, and then a detailed analysis of digital down conversion of the working principle described in the realization of digital down conversion, the design used in high-performance filters--- CIC filters and multi-phase extraction filter structure and principle. Finally, with the adoption of Simulink for digital down-conversion performance of the simulation. In the simulation based on the use of Insight s FPGA development system is measured using the test circuit of the digital down-conversion of)

EV10AQ190A配置程序 EV10AQ190A configuration program(EV10AQ190A configuration program)