Synopsys使用基本步骤使用的集成工具，有用的好东西

说明：  4位加法器，4位数字相加及进位功能的实现，主要利用Verilog语言实现，简单轻松，且代码量少(a adder which can realize 4 bit numbers adding)

block-LDPC 译码VHDL 源代码(block-LDPC decode VHDL source)

说明：  SDRAM控制，通过VHDL语言编写可运行至133MHz。(SDRAM control, written in VHDL language, can run to 133MHz.)

32位/33M 从模式(target)PCI接口参考设计，Lattice提供。由于PCI时序较复杂，此设计仅能供参考-32/route from the model (target) PCI reference design, Lattice provided. Because PCI timing more complicated, and the design for reference only

本设计是基于EP4CE15F17C8N和12864液晶的频率计程序(The design is based EP4CE15F17C8N and 12864 LCD frequency meter program)

时钟分频代码，PWM产生 RTL 源代码。(clock divider，PWM generator RTL Source Code)

华为经典设计全套入门技巧，面试经验，设计技巧(Huawei Classic Design Complete Introduction Skills, Interview Experience, Design Skills)

polyphase fir dilter

说明：  通过SPI接口实现FPGA和MCP2515独立CAN芯片通信，功能使用modelsim仿真，实现了配置、接收、发送功能。(The communication between FPGA and MCP2515 independent can chip is realized by SPI interface. The function is simulated by Modelsim, and the function of configuration, receiving and sending is realized.)

verilog实践 elc_clock 电子时钟设计(Verilog design practice elc_clock electronic clock)