Synopsys使用基本步骤使用的集成工具，有用的好东西

A multiplier unit in VHDL

FPGA数字信号处理实现原理及方法的例程(FPGA digital signal processing principle and method routines)

本程序实现流水线功能，您可根据自己需要更改参数，试用芯片xilinx，用verilog语言编写(This program implements the pipeline, you may be required to change the parameters according to their own try xilinx chip with verilog language)

利用verilog驱动LCD1602 本实验是用LCD1602显示英文。（LCD带字库）(//Use verilog driver LCD1602// video tutorial for all of us 21EDA e-learning board// The experiment is LCD1602 display in English. (LCD with font))

考研复试口语，适合计算机专业考研复试口语专业课(Traditional Interview spoken, spoken for Specialized Computer Traditional Interview)

利用FPGA开发板的PCIE接口实现数据的传输和发送。(Using the PCIE interface of FPGA development board to realize data transmission and transmission.)

串口模块程序，可以实现串行发送和接收功能，比特率可以不断调整，数据的长度是可以改变的-Serial port module program, you can achieve the serial send and receive functions, and bit rate can be continuously adjusted, the data length can be changed

关于5-11APSK在高斯信道中的误码率分析仿真程序，对具体调制方式及解码方式都有详细的过程(About 5-11APSK in Gaussian channel bit error rate analysis simulation program, has a detailed specific modulation and decoding process)

24,60,100进制的计数器，还有数字时钟，欢迎下载哦~-24,60,100 229 of the counter, digital clock also welcome to download oh ~

通过串口发送，实现FPGA与stm32的dds发生器(Implementation of DDS generator)