Synopsys使用基本步骤使用的集成工具，有用的好东西

通过编写verilog语言完成数据的在液晶LCD1602显示(By writing verilog language to complete the data displayed on the LCD LCD1602)

MP3解码的ASIC全部过程，包换含c和vhdl代码，样例。(MP3 decoding ASIC whole process, shifting with c and vhdl code, sample.)

该源码可基于FPGA设置多分辨率的HDMI显示，且其包含了完整的时序和端口、地址映射，可以很方便的将其移植(The source code can be set based on FPGA multi-resolution HDMI display, and it includes a complete timing and port, address mapping, it can be easily transplanted)

C语言写得FIR滤波器代码，简单实用，是学习滤波器设计的好材料，附带PPT滤波器设计说明(C language written FIR filter code, simple and practical, is a good learning materials of filter design, with PPT filter design )

使用信号功率计算，检测信号是否到达。从而控制后续模块，以减小系统功耗。(Signal power calculation, the detection signal to reach. To control follow-up modules to reduce system power consumption.)

使用vhdl语言实现对led的控制，还有电路仿真-Using vhdl language implementation of the led control, as well as circuit simulation

本实验是用LCD12864显示英文 显示 Our FPGA EDA NIOS II SOPC FPGA(This experiment is shown in English with LCD12864 display Our FPGA EDA NIOS II SOPC FPGA)

说明：  数电实验FPGA verilog代码，包括秒表、全加器、半加器等。(FPGA Verilog code for digital experiment)

关于LDPC解码的verilog程序，包含设计代码和验证环境(LDPC decoding on verilog procedures, including the design code and verification environment)

说明：  华为经典设计全套入门技巧，面试经验，设计技巧(Huawei Classic Design Complete Introduction Skills, Interview Experience, Design Skills)