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svpwm3
基於空間向量調變的開關法,在於載波做比較切出方波再送至開關讓馬達啟動(Based on the switching method of space vector modulation, the square wave is cut out for carrier comparison and sent to the switch to start the moto)
- 2019-01-04 16:07:37下载
- 积分:1
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ptos
八位并行数据转换为串行数据依时钟信号串行输出(Eight bit parallel data to serial data)
- 2018-05-02 19:43:25下载
- 积分:1
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font6x8
Fonts for LCD 162x64 (6x8)
- 2012-09-05 07:06:05下载
- 积分:1
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基于fpga的多功能数字时钟的实现,已经编译过了,绝对可行
基于fpga的多功能数字时钟的实现,已经编译过了,绝对可行-fpga-baseed clock
- 2022-02-04 17:16:32下载
- 积分:1
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qianzhaowang
一个简单的千兆以太网UDP协议的实现,可以实现数据的收发和ARP,实现PC端与FPGA的以太网通信(A simple implementation of Gigabit Ethernet UDP protocol can realize data sending and receiving and ARP, and realize Ethernet communication between PC and FPGA.)
- 2019-01-21 17:18:13下载
- 积分:1
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based-on-fpga
基于fpga的电子血压计。pdf文档,好用,内容清楚简单,转载而来(Electronic sphygmomanometer based on fpga)
- 2013-12-05 10:57:22下载
- 积分:1
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top
说明: FPGA程序的top.v文件,主要实现DDS信号发生器功能,通过定时器,可简单实现输出幅值无极跳变(FPGA procedures top.v documents, the main function of DDS signal generator, through the timer can be simple to achieve the output amplitude wuji hopping)
- 2008-12-05 16:18:28下载
- 积分:1
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rtl
基于脉动结构的有限域乘法器,verilog代码(Based on the pulse of the structure of finite field multipliers, verilog code)
- 2010-01-04 11:48:50下载
- 积分:1
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完成的是RS422信号的计数功能,并产生一定的触发信号
完成的是RS422信号的计数功能,并产生一定的触发信号-RS422 signals the completion of the count function, and produce a certain trigger signals
- 2022-04-14 14:08:50下载
- 积分:1
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AHB_to_Wishbone_Verilog
说明: 该源代码包是AHB总线到Wishbone总线的交接器,包括以下4个部分:RTL源代码,测试平台,软件测试程序,说明文档。(This source package is the AHB bus to Wishbone bus bridge(wrapper).It has the following 4 parts: RTL codes, testbench, software simulating files, help documents.)
- 2021-01-22 14:48:40下载
- 积分:1