TR0114 VHDL Language Reference

Xilinx 的DDR SDRAM控制器，用Verilog HDL描述- A DDR SDRAM contraller sample descripte in Verilog HDL ,base on Xilinx FPGA

this project is about FIR FIlter By VHdl codes in the ISE.

原理图和程序，都已经调试好了！可以直接使用！

VHDL cyclic redundancy check generator und receiver

verilog实现的1024位的大数模逆算法，引入RAM作为数据通道-verilog to achieve the 1024 Modular inverse algorithms, the introduction of RAM as a data channel

AUDIO音频模块AN831的录音及播放FPGA代码，测试通过(AUDIO audio module AN831 recording and playback of FPGA code, the test passed)

只需要FPGA两个通用管脚，就可以实现FPGA与PC机进行以太网通信！！如果你有ALTERA_DE1的开发板，可以直接下再看效果，用其他板子就要重新分配一下管脚，推荐使用电流输出。-Only two general-purpose FPGA pins, you can realize FPGA and Ethernet PC machine! ! If you have ALTERA_DE1 development board, you can look under the direct effect, with other board you will need to reconsider the distribution of pins, recommended the use of current output.

使用Altera公司的FPGA进行VHDL开发。使用quartus2 9.0软件在EP1C3T144C8开发板上用硬件描述语言实现一个ROM存储器。-The use of Altera" s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 development board with hardware description language to achieve a ROM memory.

led学习控制l44444444444444(led verilog led ccccccc)

ADC7606的驱动代码，采用verilog实现(ADC7606 driver code, using Verilog to achieve)