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LDPC-long40rate0.5-encode-and-decode
LDPC的短码,码长为40速率为0.5的LDPC码的设计,用的是QC矩阵,压缩文件为原码部分,工程太大传不上去。(LDPC short code, a code length of 40 rate of 0.5 LDPC code design, using a QC matrix, the compressed file is part of the original code, do not pass up the works too.)
- 2013-07-01 09:28:47下载
- 积分:1
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PID
说明: 利用Verilog语言实现PID增量式控制,输出占空比(Using Verilog language to realize PID incremental control and output duty cycle)
- 2020-04-24 10:06:59下载
- 积分:1
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PWM
基于FPGA的PWM控制器设计,包含ADC0820模块,按键扫描,PID,PWM控制器等模块,VHDL语言完成,已仿真通过(PWM controller design based on FPGA, including ADC0820 module, key scan, PID, PWM controllers and other modules, VHDL language completed, through simulation)
- 2016-05-01 15:05:58下载
- 积分:1
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uart
用Verilog HDL,实现的FPGA串口调试程序,已经在硬件上调试成功(With Verilog HDL, FPGA serial debugger implemented in hardware debugging has been successful)
- 2015-07-23 15:24:12下载
- 积分:1
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系统设计
说明: 基于旋转编码器和LED灯组的强度调节系统设计(Design of Intensity Regulation System Based on Rotary Encoder and LED Lamp Set)
- 2020-06-21 02:00:01下载
- 积分:1
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my_booth_mp
booth algotihm verilog design and test
- 2016-06-14 16:02:10下载
- 积分:1
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upp 接口,verilog
FPGA之间通信,或者FPGA和DSP之间通信的接口协议,用verilog代码编写,验证可用!
- 2022-05-05 12:14:52下载
- 积分:1
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Harris-algorithm-based-on-FPGA
在利用FPGA的并行处理能力应对高速数据和去做复杂的数据处理时,对一些较为复杂或者重复性工作模块多的情况下,算法资源就需要进行预评估。有效的资源预评估不仅可以在芯片选型上有益,还可以对程序有较详细的估计,在硬件不变的前提下能够选择更好的算法优化。本文着重在Harris算法在FPGA的实现以及在移植之前对其占用的FPGA资源进行预评估。(Response to high-speed data and do complex data processing in the FPGA parallel processing capabilities, to cope with some of the more complex or repetitive tasks module,it is necessary to pre-assessment algorithm resources. Resources pre-assessment can not only be useful in the chip selection, but also be a more detailed estimate of the program to be able to choose a better algorithm optimization in the same premise hardware. This article focuses on the pre-assessment in the Harris algorithm in the FPGA implementation and its FPGA resources occupied prior to transplantation.)
- 2013-02-28 15:41:39下载
- 积分:1
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FPGA锁相环实验
说明: FPGA锁相环实验:
顶层文件加底层IP文件构成
top中例化ip核pll(Experiment of Phase-Locked Loop Based on FPGA)
- 2020-06-22 04:00:01下载
- 积分:1
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vendingmachine
vendingmachine vhdl code
- 2011-12-03 20:53:39下载
- 积分:1