增强的音频工程

xilinx公司的virtex-5开发板原理图 需要的可以下载看一下 希望对你有帮助(xilinx company virtex-5 development board schematics can download look you want to help)

基于FPGA的快速中值滤波算法,主要使用的语言是verilog 本文没有程序(FPGA-based fast median filtering algorithm, the main language used in this article does not process verilog)

EEPROM 的verilog仿真模型（cat24cxx系列）(verilog simulition Model of EEPROM,include cat24cxx)

FPGA设计攻略及流程，包含时序收敛和引脚约束(FPGA design strategy and process, including time series convergence and pin constraints)

四轴动力模块，用一个顶模块控制，输入有：油门（20档）；指令；水平仪控制指令，4个输出口(Axis power modules, with a top module control inputs are: accelerator (20 files) instruction Level control instructions, four output ports)

基于fpga的正弦波发生器设计，有一定的参考价值，写的比较详细-The sine wave generator based on FPGA design, have a certain reference value, a more detailed written

利用ITU656接口传输数据流的方法!已得到应用!(ITU656 interface transfer data streams using the method! Has been applied!)

该程序实现的是10进制的计数器，具有置位复位的功能。-the program is the band of 10 counters, with the home-reset function.

Paint for SPARTAN 3E

压缩包是ti xds100v3 Design kit的安装文件，安装后有原理图、PCB文件，与DSP接口采用FPGA，安装后有源码，是VHDL格式的，支持开源，降低开发成本(Compression package is ti xds100v3 Design kit installation file after installation schematics, PCB files, and DSP interface with FPGA, after installation source is VHDL formats, support for open source, reduce development costs)