ByteBlasterII 下载线的制作

1。源文件保存在src目录，QII的工程文件保存在Proj目录； 2。程序实现的功能是在VGA显示器上显示彩色条纹，共8种颜色， 可以使用嵌入式逻辑分析仪观测信号； 3。modelsim仿真文件在proj--simulation--modelsim中(1. The source file is saved in the src directory QII project file is saved in the directory Proj 2. The functionality of the program is displayed on a VGA monitor color stripes, 8 colors, you can use the embedded logic analyzer observed signals 3. the modelsim simulation files in the proj- simulation- modelsim)

说明：  本文详细描述了SSI协议的通讯格式、原理及应用电路,并采用verilog语言实现了SSI通讯协议.设计实用电路并实现了与绝对值编码器的通讯(SSI protocol described in detail the communication format, principle and application circuit, and use verilog language of the SSI protocol. Practical circuit design and implementation of the communication with the absolute encoder)

尊敬的先生：，

用VHDL实现视频控制程序(实现对图像的采集和压缩)-Using VHDL video control procedures (the achievement of the image acquisition and compression)

FFT vhdl generic: I m new to vhdl, and I tried to use xilinx fft core, but when I try to simulate it in test bench using ise simulator, I get zero results. here is what I do: 1- from core generator I choose fft core and create .vhd & .vho & .xco files. 2- I add the .xco & .vhd files to my project. 3- I create a new vhdl source as a wrapper to the core and add the code from the .vho files where it exactly says, and take the ports of the component and add it to the entity of the wrapper file.-FFT vhdl generic: I m new to vhdl, and I tried to use xilinx fft core, but when I try to simulate it in test bench using ise simulator, I get zero results. here is what I do: 1- from core generator I choose fft core and create .vhd & .vho & .xco files. 2- I add the .xco & .vhd files to my project. 3- I create a new vhdl source as a wrapper to the core and add the code from the .vho files where it exactly says, and take the ports of the component and add it to the entity o

VHDL_ 两个电路计数上 / 下液晶显示语言 VHDL (海 mạch đếm lên/xuống hiển 施耐液晶 bằng ngôn ngữ VHDL)

用于FPGA实现单总线测温电阻DS18b20时序。在xilinx spartan 3中试过。-failed to translate

节约资源型 8位*8位 运算VHDL代码，采用串行运算，8 个时钟周期完成一次运算。QUARTUS下已验证(resource conservation-8* 8 Operational VHDL code, using serial computation. 8 clock cycles to complete an operation. QUARTUS has been under test)

基于FPGA与LM4550B的AC97软声卡VHDL语言驱动，版本2.0-FPGA-based soft and LM4550B the AC97 sound card driver VHDL language, version 2.0

七人表决器，当有四人或四人以上的人同意是，表决通过。每个裁判控制一个开关，高电平表同意，在quartusII上用全加器来实现，当表决通过时，实验箱上的LED灯亮