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软件开发环境ISE 7.1i仿真环境:ModelSim SE 6…
软件开发环境:ISE 7.1i
仿真环境:ModelSim SE 6.0
1. 这个实例实现通过ModelSim工具实现一个具有“百分秒,秒,分”计时功能的数字跑表;
2. 工程在project文件夹中,双击paobiao.ise文件打开工程;
3. 源文件在rtl文件夹中,paobiao.v为设计文件,paobiao_tb.tbw是仿真测试文件;
4. 打开工程后,在工程浏览器中选择paobiao_tb.tbw,在Process View中双击“Simulation Behavioral Model”选项,若正确安装ModelSim,系统将自动打开ModelSim进行行为仿真,运行仿真即可得到仿真结果。-Software development environment: ISE 7.1i simulation environment: ModelSim SE 6.01. Realize this instance through the ModelSim tool realize a
- 2022-02-19 23:39:17下载
- 积分:1
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Uart2Sdram2TFT_RGB2GRAY
说明: 使用FPGA实现RGB图像转灰度图像的算法,下载入自己的电路板可直接将摄像头拍摄到的图像实时转换成灰度图像(FPGA is used to realize the algorithm of transforming RGB image into gray image. The image captured by the camera can be converted into gray image in real time by downloading it into its own circuit board)
- 2019-12-30 19:42:58下载
- 积分:1
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基于VHDL可编程BPSk调制教学~~~十分好用`~容易学会
基于VHDL可编程BPSk调制教学~~~十分好用`~容易学会-VHDL-based programmable BPSk modulation of teaching is very good ~ ~ ~ `~ easy to learn to
- 2023-05-08 13:45:02下载
- 积分:1
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EDA常用计数函数VHDL程序设计,减法计数器:可预置数:
EDA常用计数函数VHDL程序设计,减法计数器:可预置数:-common counting function EDA VHDL programming, subtraction counter : Preset :
- 2022-03-25 01:33:15下载
- 积分:1
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DLX-pipeline-in-verilog
verilog实现DLX指令集5段流水线(5 stage DLX pipeline implemented in verilog)
- 2013-08-24 22:59:48下载
- 积分:1
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VHDL实现ALU的源代码,并且提供了一个详细的testbench!
VHDL实现ALU的源代码,并且提供了一个详细的testbench!-ALU VHDL source code, and provide a detailed testbench!
- 2022-03-12 21:14:39下载
- 积分:1
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ht66f0185-1
小家电常用芯片HT66F0185的UART 使用例子,已在产品使用(Small appliances commonly use UART chip HT66F0185 of example, has been used in products)
- 2020-10-09 16:27:34下载
- 积分:1
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aulap3_IsadoraStangarlin
Code developed in classroom
- 2017-09-28 00:51:06下载
- 积分:1
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用VHDL语言编写的写存储器程序,可下载在FPGA中使用
用VHDL语言编写的写存储器程序,可下载在FPGA中使用-VHDL language used to write memory program can be downloaded in the FPGA using
- 2022-06-17 11:46:31下载
- 积分:1
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gps
基于fpga和dsp架构的gps接收机的设计和实现(Design and Implementation of gps Receiver Based on fpga)
- 2017-05-25 17:44:51下载
- 积分:1