VGA图象显示控制器设计,实现在VGA显示器上显示图象.

FFT变换的IP核的源代码 VHDL~-FFT IP core of the source code for VHDL ~

VHDL实现的超前进位加法器-the VHDL-ahead Adder

实现大型LED屏显示的CPLD程序，对FPGA学习很有帮助-To achieve large-scale LED screen display of the CPLD program, very helpful for learning FPGA

I2C IP for Quartus V9.0 sp2, can used in SOPC builder.

贪吃蛇程序，用verilog实现，可以运行只要修改一下相应的FPGA芯片类型和VGA接口相应的引脚(Snake program, using Verilog to achieve, you can run as long as the appropriate to modify the corresponding FPGA chip type and VGA interface to the corresponding pin)

这一设计实例深入浅出，介绍怎样产生一个Qsys子系统。 您将产生一个含有以下组成的Qsys系统:在Cyclone IV GX收发器入门套件上,设计带嵌入式收发器的Gen1×1硬核IP的 PCI Express IP编译器。 (Qsys system: the Cyclone IV GX Transceiver Starter Kit, designed with embedded transceivers Gen1 × 1 hard IP PCI Express IP compiler.)

d flip flop t flip flop counter mux using active hdl can be run using 3.2 version and creating new design

改写四号中断的 自己编的，，，，，，求过啊！！！一个很简单的小程序(Rewrite the fourth interruption of their series,,,,,, begged ah! ! ! A very simple little program)

sd_sdram_lcd 是读取SD卡中的数据，然后通过LCD显示(It is to read the data in SD card and display it by LCD)

状态机的性能考察.rar 状态机的性能考察.rar-Study the performance of state machine. Rar inspect the performance of state machine. Rar