dds在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过...

基于ALTERA AVALON BUS 的 VGA Controller 设计(ALTERA AVALON BUS VGA Controller )

基于CPLD 的光电脉冲码盘 信号四倍频电路设计-CPLD-based electro-optical pulse encoder signals four multiplier circuit design

本实验为UART回环实例，实验程序分为顶层unrt_top、发送模块uart_tx、接收模块 uart_rx，以及时钟产生模块clk＿div。uart＿rx将收到的包解析出8位的数据，再传送给 uart_tx发出，形成回环。参考时钟频率为100MHz，波特率设定为9600bps。(This experiment is an example of UART loop. The experimental program is divided into top-level unrt_top, sending module uart_tx, receiving module uart_rx, and clock generation module clk_div. Uart_rx parses the received packet into 8 bits of data and sends it to uart_tx to send out, forming a loop. The reference clock frequency is 100 MHz and the baud rate is set to 9600 bps. stay)

pci协议主模块开发实用代码， 适合初级学习者使用 很不错(pci agreement to develop practical code, very good for junior learners)

spartan-3e vhdl fpga 输入用滑动按钮代替 输出用led代替(spartan-3e VHDL fpga input with sliding button instead of the output with led instead)

四位密码锁，移位显示，可以设置和更改密码。-4 lock, shift, it can be set up and change your password.

verilog编写实用多功能电子表-Verilog prepared practical multi-function electronic Table

用Verilog HDL语言进行HDB3编码，并通过Quartus Ⅱ仿真验证(With the Verilog HDL language HDB3 coding, and simulation by Quartus Ⅱ)

一个比较有参考价值的sram IP核，对SOPC感兴趣的人士有一定的指导意义！该程序是采用avalon总线，可以直接内嵌进SOPC Builder。-A comparison reference value has sram IP core, on the SOPC interested people have a certain guide! The procedure is used avalon bus, can be directly embedded into the SOPC Builder.

正弦波UPS中的逆变电路 包括原理分析 框图 及原理图(Sine wave UPS inverter circuit the principle analysis block diagram and schematic)