dds在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过...

VHDL tutorial for beginning learner

几大代工厂的flash verilog源代码(flash verilog code)

介绍分频器的好资料。不光有奇数分频、偶数分频，还有小数分频。相信把这个资料理解透了后以后分频器的设计就不是问题了。(Introduction divider good information. Not only have an odd frequency, even frequency, there are fractional. I believe understanding this information through the post after the Divider is not a problem.)

电子秒表，FPGA实现,本科某课程设计，程序注释非常详细，(FPGA TIME-COUNTING)

说明：  实现24小时计时，因为位数不够，这里是12进位，可自行调整进位数(Realize 24-hour timing, because the number of digits is not enough, here is 12 carry, you can adjust the carry number by yourself.)

说明：  一维超混沌随机数的生成verilg，还有testbench仿真激励，modelsim的仿真工程。(The generation of one-dimensional hyperchaotic random number verilg, testbench simulation stimulation and Modelsim simulation engineering.)

基于FPGA 的12864液晶显示汉字，用verilog编写的。(12864 liquid crystal display Chinese characters based on FPGA, written in verilog.)

基于FPGA的频率测量，能测量方波信号的频率、占空比、相位差。范围100mHz~200MHz，精度0.0001Hz(The frequency measurement based on FPGA can measure the frequency, duty cycle and phase difference of the square wave signal. Range 100mHz~200MHz, precision 0.0001Hz)

四轴动力模块，用一个顶模块控制，输入有：油门（20档）；指令；水平仪控制指令，4个输出口(Axis power modules, with a top module control inputs are: accelerator (20 files) instruction Level control instructions, four output ports)

伪随机序列FPGA 通过仿真 M3000(Pseudo-random sequence M3000 FPGA simulation)