dds在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过...

哈希算法FPGA实现代码，采用MD5算法，并给出了仿真波形。(MD5 hashing algorithm for FPGA implementation code)

SystemVerilog For Design (Springer-2nd_Ed-2006)

数控分频器设计:对于一个加法计数器，装载不同的计数初始值时，会有不同频率的溢出输出信号。计数器溢出时，输出‘1’电平，同时溢出时的‘1’电平反馈给计数器的输入端作为装载信号；否则输出‘0’电平。 -NC divider design : an adder counter, loading the initial count value, have different frequency output signal of the overflow. Counter overflow, the output"1 "Level, Overflow at the same time the"1 "level feedback to the counter input signal as loading; Otherwise output"0 "level.

比较适合初学学者，而且比较基础。描述的不全面，先看看吧-it‘s best book for beginner！

8051IP 核源代码（VHDL）.RAR-8051IP nuclear source code (VHDL). RAR

说明：  VGA图像显示，可实现图片和实现移动功能(VGA image display, enabling images and moving functions to achieve)

8051IP 核源代码-8051IP nuclear source code

主要介绍了ＦＰＧＡ设计的基本原则、基本设计思想、基本操作技巧、常用模块。-Mainly introduces the basic principles of FPGA design, basic design concepts, basic operating skills, commonly used modules.

能产生正弦波、三角波、方波和e指数衰减的扫频波，且相关参数可调(Can produce sine wave, triangle wave, square wave, and e exponential decay wave sweep and adjustable parameters)

异步串行传输的verilog hdl 功能文件以及测试文件(The verilog hdl source and the testbench of asynchronous serial transmission )