A Dec example written in VHDL.

异步串行传输的verilog hdl 功能文件以及测试文件(The verilog hdl source and the testbench of asynchronous serial transmission )

有关FPGA芯片的管脚的封装的一些资料。-Pin on the FPGA chip packaging some of the information.

VHDL code comparator

《编写VHDL测试概述》的英文原版讲述了如何使用VHDL写测试凳程序("Writing VHDL test overview" of the English original to write about how to use VHDL test bench program)

FPGA Verilog HDL模拟IIC通讯接口-FPGA Verilog HDL IIC Interface

红绿灯交通灯的设计，通过规定时间红绿灯的转变实现交通灯的控制(Traffic light traffic light design, implementation, control traffic lights traffic light changes by a predetermined time)

篮球24s计时器，元器件简单，功能复杂。满足小型计时需要。

FFT程序，此程序虽然耗逻辑资源很大，但是在接受数据后的第7个时钟沿就可以输出FFT变换后的数据，对要求时延较低的系统可以考虑-FFT procedure, this procedure should not consume a lot of logic resources, but the data in the first seven clock can be output along the FFT transformed data, the requirements of time-delay system can be considered lower

JOP的内核文件，这是核心的核心，中文资料基本找不到-JOP kernel, which is the core of the core, the Chinese can not find basic information

检测上升沿的verilog程序，有验证程序，可用synplify验证-Detection of rising edge of the Verilog procedures, there is the verification process can be used to verify Synplify