This code implements the output shift register functions, beginners can learn to...

传感信号无线数字传输系统的设计与实现.kdh(err)

用verilog编写的科斯塔斯环，希望有帮助(Costas loop written in verilog helpful)

基于fpga的verilog实现ad及uart，并进行仿真验证(Verilog based on FPGA implements AD and uart, and carries out simulation verification)

单相的主动式电压质量控制器 对电压跌落进行了补偿(single-phase AVQR for power quility improvement)

morris mano basic vhdl code in ise

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基于sopc的7352的ad模块的nios软核多通道编写,verilog 写的(The sopc 7352 AD module nios soft core multichannel write. Rar )

HDLC控制器源码，包括单独HDLC的Tx端和Rx端实现，以及顶层带FIFO和Wishbone总线控制器的实现，通过Wishbone可方便与CPU连接，通过软件控制整个HDLC控制器的工作。

用vhdl语言编写的16bit的REG代码，以及iv，not and2，rca，fa，alu，acc，lfsr，mux21.

verilog code,about oc8051