采用systemc语言设计了一个状态机，主要包括两个进程，仿真结果表明状态机可以正常工作...

fpga串口的接收程序基于verilog语言拿走不用谢。(The receiving program of FPGA serial port is based on Verilog language.)

8051核的vhdl原代码。-8051 core VHDL source code.

多倍（次）分频器 请注意: 本例的各个源描述的编译顺序应该是: 52_divider.vhd 52_divider_stim.vhd (Times (times) divider Please note: This case is described in various sources to compile the order should be: 52_divider.vhd 52_divider_stim.vhd)

这是在 vhdl 的简单循环的拳头在后进先出队列。缓冲区的大小和数据大小可以通过 N 和 W 的参数配置。队列最前面的是可用输出数据。两个信号控制写入和读取数据。如果缓冲区是空的还是满的两个输出信号信息。

the 8 bit alu by verilog

Implement LMS vhdl code.

VHDL黄金版，本人费了九牛才找到，帮助初学者入门-VHDL version, I spent nine cattle to find help beginners entry

说明：  自己设计的一个其人投票系统，对于VHDL初学者可以参考下(One of their own design their human voting system, for VHDL beginners can refer to the following)

一种基于FPGA的通用微处理器设计-A general-purpose FPGA-based microprocessor designs ....

nios学习资料，fpga调用外部sdram实例，值得初学者下载。(nios learning materials, fpga call external sdram instance, it is worth beginners to download.)