采用systemc语言设计了一个状态机，主要包括两个进程，仿真结果表明状态机可以正常工作...

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It is the FSM implemented in Xylinx 14.7 on FPGA

六十进制计数器，显示0到60.可以用数码管显示。(Six decimal counter 0-60 can use the digital display.)

说明：  VHDL BASED DATA COMPRESSION

说明：  MATLAB to HDL Code conversion

Five day stmicroelectornics vhdl training presentation

4. If a modified source code is distributed, the original unmodified -- source code must also be included (or a link to the Free IP web -- site). In the modified source code there must be clear -- identification of the modified version.-4. If a modified source code is distributed, the original unmodified-- source code must also be included (or a link to the Free IP web-- site). In the modified source code there must be clear-- identification of the modified version.

modelsim设计的可调占空比的方波程式-modelsim designed adjustable duty cycle of the square wave program

定时器的编程，vhdl语言，可以实现24时制定时器-Timer programming, vhdl language, can be achieved when the system timer 24

我用的是二进制分频的方法，这种分频方法的分频只能是2n次方，有限制，但是很方便