采用systemc语言设计了一个状态机，主要包括两个进程，仿真结果表明状态机可以正常工作...

用全加器设计8位运算器逻辑电路图 2、根据逻辑电路用 VHDL编程实现 3、调试编译通过后，仿真 (this file can help you learn the design of cpu)

tms320c6747的测试程序 。用于dsp各个模块的测试，很好的例子(dsp tms320c6747)

UART功能,可以增加在NIOS2內,主要來做外部Flash的擦除及寫入,需搭配上位機傳輸字串來控制(UART function, can increase the NIOS2, the main external Flash to do the erase and write, to be a string with the host computer to control the transmission)

说明：  数字逻辑实验课第十二次作业，基于Verilog的Clock时钟(Clock based on Verilog)

基于IP核RAM的同步fifo设计，工程使用Xilinx的开发软件ISE(RAM-based synchronization fifo IP core design, engineering, software development using Xilinx ISE)

利用VHDL语言和模块化设计实现PCM编译码的功能，整体工程和代码全有。(PCM encode and decode by VHDL in Quartus2. )

spartan-3e fpga vhdl 实现的计数器 记满后点亮小灯(spartan-3e fpga vhdl counter to light led)

在xilinx的ml507板子上用的ICAP功能 配置存储器 这里边包含了控制程序 以及配置ICAP寄存器的程序 就是完整的通过串口控制FPGA多重配置的程序 用verilog实现的(how to configure the ICAP)

单周期16位CPU的设计,我们的计算机组成原理课设，可以实现R型、I型和J型指令，内有报告和指导书(Single-cycle 16-bit CPU design, our Principles of Computer Organization class set, you can achieve R-type, type I, and J-type instructions, reports and instructions)

design and implementation of a format conversion system on the Altera NIOS board(QUARTUS) which reads an analogue input, converts it into digital data, and then does the reverse conversion back into analogue format. This will be done by taking an analogue an analogue input using SPI MCP3202 12-Bit A/D converter to generate the digital data stream and then the digital data will be used to generate an analogue output using Analog Devices 8-bit SPI AD7303 D/A converter.