采用Verilog HDL硬件语言设计,实现基本的公用电话计费功能,设计完整....

该项目是用VHDL编写的，并在Nexys2板套件的4个七段显示器中显示一个测微计的秒、分和小时。时间可以在开关0中停止，在按钮0中复位。显示方式与显示方式不同最小：分段到hr:min通过切换开关1

全加器的vhdl程序及其仿真图像.by利用它可以方便、准确地得到输出

FPGA 学习实例 动态时钟、面积、速度优化相关代码(Codes related to dynamic clock, area and speed optimization for learning examples of FPGA)

Synopsys® Timing Constraints and Optimization User Guide

verilog 双模块算术平均值计算模块，子模块在时钟上升沿技术，高层模块根据当前计数值计算算数平均(verilog double module arithmetic mean calculation module, sub-module in the clock rising edge technology, high-level module is calculated based on arithmetic average of the current count)

串口收发程序，成功通过仿真，可以用来学习(Serial transceiver,It is successful through simulation and can be used to learn)

大名鼎鼎的Synopsys公司出的8051IP Core VHDL语言编写，能被keilC51支持-famous Synopsys Core 8051IP the VHDL language, can be supported keilC51

用vhdl编写的简易电子中设计，经过测试成功，且用记事本上载，无需阅读器进行阅读。-Use of VHDL in the preparation of simple electronic design, has been tested successfully, and use Notepad to upload without reader reading.

四位密码锁，移位显示，可以设置和更改密码。-4 lock, shift, it can be set up and change your password.

目前最新的OVL库，里面是标准的ASSERTION模块，支持VHDL刚Verilog，最近在做AXI协议验证的时候用到，分享下(The latest OVL(open verification library),including all standard module of assertions(VHDL and Verilog). It can be used into AXI Protocl Verification. Just share with you guys.)