-
alu
the 8 bit alu by verilog
- 2011-05-26 11:25:43下载
- 积分:1
-
5_ADC_Lab
基于altera公司MAX10型FPGA的ADC调试程序(ADC-based debugger altera company MAX 10 type of FPGA)
- 2015-11-18 10:56:16下载
- 积分:1
-
加法器
说明: 4位加法器,4位数字相加及进位功能的实现,主要利用Verilog语言实现,简单轻松,且代码量少(a adder which can realize 4 bit numbers adding)
- 2020-10-31 11:05:41下载
- 积分:1
-
FPGA realization of DDS with the schematic diagram, structural clarity, the use...
用FPGA实现DDS的原理图,结构清晰,采用总线方式与外部单片机通信-FPGA realization of DDS with the schematic diagram, structural clarity, the use of bus-way communication with the outside Singlechip
- 2022-04-16 10:26:17下载
- 积分:1
-
verilog-SPI-core
用VerilogHDL写的spi 核的例子(A simple example of SPI core using Verilog HDL)
- 2011-08-31 20:37:07下载
- 积分:1
-
UML_2_Pour_les_bases_de_donnees
UML2 apprendre a modeliser a l aide de UML
- 2014-02-25 01:32:23下载
- 积分:1
-
FPGA7人表决器
–ABCDE五路输入表示五人的选择,同意为1,不同意为0,以开关形式实现
–有半数以上同意绿灯亮,否则红灯亮。即分别对应输出Y、R为1或0
–参考仿真结果图:10ns|20ns|30ns|40ns|50ns
- 2022-10-01 22:45:03下载
- 积分:1
-
My-Simple-Specturm--Analyzer
基于LabVIEW FPGA的频谱估计与分析(the power spectrum estimation and analysis based on LabVIEW FPGA)
- 2013-11-13 08:45:40下载
- 积分:1
-
sdram-source
SDR SDRAM 控制器的源代码 altera公司的(source code from altera)
- 2010-06-09 19:35:03下载
- 积分:1
-
multiplier
参数可配置的sequential 乘法器和booth 乘法器(verilog source code with configurable parameters for sequential multiplier and booth multiplier )
- 2011-12-08 15:14:04下载
- 积分:1