VHDL版的C51核(MC8051)

利用VHDL实现CPLD（EPM240T100C5）的串口发送程序-Using VHDL realize CPLD (EPM240T100C5) Serial sending procedures

4X4 KEYPAD 的输入位数计数器，可以自己定义输入的位数-4x4 KEYPAD median counter input, input their own definition of the median

基于压缩感知的ISAR方位向成像以及与FFT成像对比(CS-based ISAR imaging and RD imaging)

用vhdl语言编写的程序，可以播放乐曲，有分频模块，可播放梁祝等歌曲。

使用vhdl语言设计一位全加器，在仪器上下载并实现LED灯的闪亮(A full adder design)

能产生正弦波、三角波、方波和e指数衰减的扫频波，且相关参数可调(Can produce sine wave, triangle wave, square wave, and e exponential decay wave sweep and adjustable parameters)

8051的verilog实现，内附testbench,c语言调试程序-8051 verilog achieve, enclosing testbench, c language debugging procedures

VHDL 洗衣机程序，可实现定时、报警、洗衣，脱水等等功能。底层为VHDL文件，顶层为电路图连接

华为公司学习verilog的资料，绝密资料，想学习verilog编程，想学习FPGA，想以后进华为公司的都可以看看。(Huawei learning verilog information, confidential information, want to learn verilog programming, want to learn FPGA, think later into the Huawei can see.)

前导零的计算 (Calculation of leading zeros)