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mig_7series_v1_9
DDR3控制器源码,针对XilinxFPGA的DDR3控制器的源码,已经验证通过。(DDR3 Controller,complete DDR3 controll,have pass verificaion.)
- 2016-08-16 09:27:43下载
- 积分:1
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RC6-block-cipher-using-VHDL
VHDL implementation of RC6 encryption algorithm
Test file represent applying all zero input and all zero key
note that result is correct but bytes positions are swapped
- 2020-12-01 22:09:26下载
- 积分:1
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Code-Verilog
this is code verilog
- 2012-05-09 22:02:56下载
- 积分:1
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交通灯控制(VHDL)!!!!!!!!!!!!!!!!!!!!!!!!!!…
交通灯控制(VHDL)-Traffic Light Control (VHDL)! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! !
- 2023-03-20 10:30:04下载
- 积分:1
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line_four
利用verilog HDL逐点比较法实现直线和圆弧插补(Use verilog HDL by-point comparison method to achieve linear and circular interpolation)
- 2020-12-01 14:59:27下载
- 积分:1
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these files are written in verilog but i am uploading in text format
these files are written in verilog but i am uploading in text format
- 2022-02-06 16:09:07下载
- 积分:1
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GgmsskModulatM
GMSK的调制解调,理理想信道,画出其功率谱。
(GMSK modulation and demodulation, management ideal channel, to draw its power spectrum.)
- 2020-07-02 02:00:02下载
- 积分:1
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izhihuangenzongPWMnb
三相电流滞环跟踪PWM逆变器。逆变电路负载电流与指令电流比较产生PWM波形。经验证可很好实现功能。(The three-phase hysteresis current tracking PWM inverter. Load current command current of the inverter circuit generating a PWM waveform. Proven functions well.)
- 2012-11-26 11:56:56下载
- 积分:1
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power_control
四轴动力模块,用一个顶模块控制,输入有:油门(20档);指令;水平仪控制指令,4个输出口(Axis power modules, with a top module control inputs are: accelerator (20 files) instruction Level control instructions, four output ports)
- 2013-12-26 20:57:03下载
- 积分:1
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计数器 0 到 9999
本程序显示在 BCD display 数从 0 到 9999.This 程序进行了智能 2 FPGA 板。
- 2022-05-08 02:50:35下载
- 积分:1