VHDL洗衣机控制器

说明：  完成对cdcm6208的时钟芯片的配置，输出高频时钟(cdcm6208 cofigure using SPI interface)

is61lv25616简单的verilog程序，完成sram读写 主要是基于FPGA(EP2C8Q208I8)下的SRAM驱动(1lv25616 simple verilog program, complete sram read and w1lv25616 simple verilog program, complete sram read)

超声波测距程序 适用传感器HC-SR04(The application of sensor HC-SR04 for ultrasonic range finder)

说明：  VHDL BASED DATA COMPRESSION

实现有限域中乘法，输入二个普通二级制数，输出在本原多项式的乘法结果(Achieve limited multiplication field, enter the number of two-tier system of two ordinary output in primitive polynomial multiplication results)

说明：  vhdl code for full adder

verilog测试，fpga测试片外sramis61lv25616，256个k个字，16位，比较难调(it is fpga is 61lv25616 simple verilog program,complete sram read and write.it can read and write .)

电梯的vhdl设计，6层楼含开关门，警报，内部请求，外部请求-Vhdl elevator design, six floors with switch doors, alarm, internal requests and external requests

verilog源码，可实现两位的加法器，在xillinx foundation 3.1下验证通过-verilog source, the two can achieve Adder, In xillinx foundation 3.1 certification through

运用Quartus在LCM中显示静态宫殿图形-Use Quartus in LCM display static graphics palace