VHDL洗衣机控制器

08EE06EDA 实验 4（VHDL 状态机设计_序列检测器）6/7/2008-design thesis requirement by vhdl

使用verilog hdl语言编程正弦波信号，能仿真出结果(Can use verilog HDL language programming sine wave signal, the simulation results )

实施256点，

protel fpga常用封装库1，非常难找的-protel fpga library a popular package is very difficult to find the

mdct, it contains DOC,MATLAB,source,synthesis.

说明：  verilog开发的经典教材，详细介绍了语法，常见历程，以及通用的程序段(verilog development of the classic materials, detailed information on syntax, common history, as well as the common program segment)

控制三相步进电机及光电编码器的采集,当电机停止时,保证三相里面只有一相相通,防止停止时电流过大.(Control three-phase stepper motor and optical encoder collection, when the motor stops to ensure that only one phase of three-phase inside the heart, and to prevent too much current is stopped.)

两个例子提醒我们如果我们要使用锁存器则不需要任何操作，如果我们想避免锁存器的话，我们要让这个元器件的每一个可能条件赋予一个值-signal or variable "" may not be assigned a new value in every possible path through the Process Statement

M25P64-SPI-FLASH芯片的FPGA控制程序，已仿真验证(M25P64- SPI- FLASH chip FPGA control program, simulation)

串口通讯，与硬件联通调试过，收发程序是分开的。(Serial Communication)