基于fpga的液晶驱动开发过程相关资料，用于借鉴和学习

altear max10 adc demo，实验使用了2个adc，最大支持18路adc(altear max 10 demo with 2 adc， max support 18 channel adc)

一个可综合的同步FIFO的verilog源代码-An integrated synchronous FIFO in Verilog source code

EEPROM 的verilog仿真模型（cat24cxx系列）(verilog simulition Model of EEPROM,include cat24cxx)

一位加法全加器，可以实现低位进位输入和高位进位输出。(full adder)

polyphase fir dilter

介绍分频器的好资料。不光有奇数分频、偶数分频，还有小数分频。相信把这个资料理解透了后以后分频器的设计就不是问题了。(Introduction divider good information. Not only have an odd frequency, even frequency, there are fractional. I believe understanding this information through the post after the Divider is not a problem.)

针对串行存储器M25P80应用的verilog程序-M25P80 serial memory for applications Verilog program

用verilog写的各种实用的分频器，很好的参考例子。-Using Verilog to write a variety of practical divider, a good reference example.

用VHDL硬件描述语言实现的对FPGA（Cyclone II）的配置的VHDL源代码。-VHDL hardware description language for FPGA (Cyclone II) configurations VHDL source code.

基于FPGA的高性能32位浮点FFTIP核的开发，适合fpga工程技术人员参考-FPGA-based high-performance 32-bit floating-point nuclear FFTIP development, engineering and technical personnel for reference fpga