VHDL语言写的频率计的程序，内带完整的技术报告

在ISE12.4与TMS320F2812的XINTF接口，实现数据收发(In ISE12.4 TMS320F2812 the XINTF, data transceiver)

用DE0开发板实现电话计费器，基本功能：可设置通话模式，能初始化话费余额，拨动开关可进入通话模式，并根据通话时间和相应通话模式扣除相应的费用。通话过程中能够通过开关切换显示通话时间和话费余额，并可暂停通话。压缩包里有详细的WORD文档的说明，包括波形仿真和DE0的引脚功能介绍。(Implemented by DE0 board telephone billing, basic function: to set the call mode, you can initiate credit balance, toggle switch into the talk mode, and deduct the cost of a call based on call time and the corresponding mode. Call talk time and can be displayed by switching credit balance, and mute. Compression bag has a detailed description of WORD documents, including the waveform simulation and DE0 pin function description.)

verilog实现ALU的源代码，并提供了一个详细的测试平台！-achieve ALU Verilog source code, and provide a detailed test platform!

基于单片机的DDS信号发生器，具有DDS思想的单片机编程。。。(Sunplus based DDS signal generator with DDS thinking microcontrollers. . .)

内置自修复分析仪

cpld/fpga积分梳状滤波器(CIC)设计-cpld/fpga Integral comb filter (CIC) design

verilog vga 图像处理(verilog vga)

本文是自已写的电子密码锁的详细开发过程，用的是Modelsim进行仿真实现，打开文档lzp-This article is written in their own electronic locks detailed development process, using a ModelSim simulation achieved, open the document lzp

Based on SVPWM three-level inverter matlab simulation, It describes the application of load forecasting, EULER numerical analysis method.

本文件是周立功试验开发板的配套资料，容易学会-This document is ZLG test development board supporting information, easy to learn