利用FPGA串口通信向上位机发送数据

基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,图像边缘提取(System Generator based image processing engineering, multimedia processing FPGA implementation source code, image edge extraction)

用verilog写的cpld的各种分频程序，希望大家指正，谢谢！-using Verilog cpld written by the various sub-frequency procedures in the hope that we stand corrected, thank you!

说明：  ZEDBOARD的管脚分配图和约束文件，包括PCB图和xdc文件(Pin assignment of ZEDBOARD)

基于VHDL的SDH专用芯片的TOP-DOWN设计， 内有全套源码以及图片，内容详尽，绝对真实可靠！(VHDL based on the SDH ASIC Design TOP-DOWN, which has a full set of source code, as well as pictures, and detailed, reliable and absolutely true!)

moving tracking based in D5M camera tracking camera

CPU代码-VHDL语言，实现了CPU的基本功能。-CPU code-VHDL language, the realization of the basic functions of the CPU.

设计一个十进制计数器，具有显示位置随计数时钟在八个数码管中左右滚动的功能。(Design of a decimal counter, a display position with the count clock in at around eight digital scrolling function.)

用verilog实现sobel边缘检测算法(sobel edge detection with verilog language)

有限状态机工作原理、设计方法、步骤等精要说明(Finite state machine working principle, design method, such as Essentials of steps to explain)

说明：  ad9361 matlab驱动代码，运行此代码可在matlab中控制AD9361(AD9361 matlab driver code, running this code can control AD9361 in MATLAB)