vhdl 计数器源程序，大家看看吧 vhdl 计数器源程序，大家看看吧...

design the connecter between dsp and sed12

vhdl golden reference guide

BCD to 7 segments display decoder

用硬件描述语言编程实现减法器,实现两个操作数的减法-Using hardware description language programming subtraction, and the achievement of the two operands of the subtraction

VHDL语言设计的秒表，实现计时功能，实现报时功能，并且通过硬件实验。-VHDL language design stopwatch, timer function of the realization, the realization of time functions, and through hardware experiments.

cache，实现了部分简单指令，仿真模拟确认可行(Single-cycle CPU, to achieve some simple instruction, simulation confirm feasible)

本设计是基于FPGA的一个FIR低通滤波器设计，要求使用Verilog语言编写滤波器模块，通过编译和综合，并通过Matlab和modelsim联合仿真验证设计结果。(This design is a FIR low-pass filter design based on FPGA, use Verilog to program filter module, and joint simulation by Matlab and modelsim to validate the design results.)

這裡提供Auto Gain Control 的詳細代碼與功能介紹(Here are details of the code and the Auto Gain Control Functions)

说明：  基于FPGA和弦！！！音乐芯片的设计与实现！！！(Design and implementation of FPGA chip based on the chord music)

xilinx 开发板程序，VGA控制显示-Xilinx development board procedures, VGA display control