24,60,100进制的计数器，还有数字时钟，欢迎下载哦~

file_read vhdl code provide by my teacher for reading file into FSM-file_read vhdl code

this file describes the steps in building a fifo buffer module in verilog hdl and programming them on an fpga device

使用verilog语言完成了基于cordic算法求反正切的计算，精度为8次迭代(Verilog language used to complete based on CORDIC algorithm for arctangent calculation, an accuracy of 8 iterations)

只需要FPGA两个通用管脚，就可以实现FPGA与PC机进行以太网通信！！如果你有ALTERA_DE1的开发板，可以直接下再看效果，用其他板子就要重新分配一下管脚，推荐使用电流输出。-Only two general-purpose FPGA pins, you can realize FPGA and Ethernet PC machine! ! If you have ALTERA_DE1 development board, you can look under the direct effect, with other board you will need to reconsider the distribution of pins, recommended the use of current output.

fpga key test 入门 xilinx 黑金的板子(fpga key test xilinx)

该PPT是一个内部教学资料，想学习EDA技术的朋友可以看看这个教学资料。-The PPT is an internal teaching materials, want to learn EDA technologies friends can look at the teaching and learning materials.

实现QAM调制功能和QAM解调功能的代码.(Realize QAM modulation function and QAM demodulation function code.)

实现图像的中值滤波功能，文件里有效果展示(The realization of the median filter function of the image, the file has the effect of display)

用verilog实现除法器，调用了ip核，不仅有源代码，还有测试程序的时序编写(verilog ise divider)

基于FPGA的16QAM调制程序,基于verilog开发环境(16QAM modulation program based on FPGA-based development environment verilog)