24,60,100进制的计数器，还有数字时钟，欢迎下载哦~

control stepper motor by fpga card with vhdl program

说明：  编码方式为213的Viterbi卷积码编码器和译码器的FPGA的实现，包含整个QuartusＩＩ的工程文件，解码方式为寄存器交换法(Encoding for the 213 convolutional code encoder and Viterbi decoder FPGA realization of the project file that contains the entire QuartusII, decoding method for the register exchange)

说明：  FPGA锁相环实验： 顶层文件加底层IP文件构成 top中例化ip核pll(Experiment of Phase-Locked Loop Based on FPGA)

turbo product code used in error correction

扰码器的FPGA实现，选择的扰码器规格为15位移位寄存器。(FPGA scrambler, scrambler specifications for a 15 bit shift register.)

序列检测VHDL源代码，ATERA平台编译。详细的报表说明和模拟源代码。

典型实例10.8 字符LCD接口的设计与实现 软件开发环境：ISE 7.1i 硬件开发环境：红色飓风II代－Xilinx版 1. 本实例控制开发板上面的LCD的显示； 2. 工程在project文件夹里面 3. 源文件和管脚分配在 tl文件夹里面 4. 下载文件在download文件夹里面,.mcs为PROM模式下载文件,.bit为JTAG调试下载文件。-Typical examples of character LCD interface 10.8 The Design and Implementation of Software Development Environment: ISE 7.1i development environment hardware: Hurricane II on behalf of the red-Xilinx Edition 1. The above examples of the control board of the LCD display 2. Projects project folder inside 3. the distribution of the source file and pin in rtl folder inside 4. download files in download folder inside,. mcs file for the PROM mode download,. bit for the JTAG debugger to download the file.

Image Embedded VHDL Code by using watermarking technique

Module for filtering input digital signal

Verilog HDL语言编写异步FIFO(Verilog HDL language, asynchronous FIFO)