Xilinx FPGA make 50 smaller

说明：  ask psk 编码调制的vhdl 实现(ask psk coded modulation to achieve the VHDL)

逐步演示试用modelsim建立仿真的过程，初学者应该看看(Step by step demonstration of the trial to establish modelsim simulation process, beginners should look at the)

verilog code for counter four

关于两种实现pwm的方法 基于51单片机设计-on two methods to achieve PWM 51 microcontroller-based design

Protocol Buffers - Google s data interchange format.

Xilinx Licenses 2018

此为华远显示320*240LCD驱动程序，该程序也适用于带RA8806控制器的LCD(This is the Huayuan display 320* 240LCD driver, the program also applies with RA8806 LCD controller)

数控分频器的设计 数控分频器的功能就是当在输入端给定不同输入数据时，将对输入的时钟信号有不同的分频比，例3的数控分频器就是用计数值可并行预置的加法计数器设计完成的，方法是将计数溢出位与预置数加载输入信号相接即可。(NC NC divider divider design of its function is when the input given different input data, input the clock signal will have different frequency than, for example 3 is to use the NC prescaler count preset value of the adder parallel counter design is completed, the method is to count the number of overflow bit with preset load to the input signal phase.)

multiplexerwe 的 vhdl 程序可以写也像 thisits 非常简单的代码为 beginers 了解 4： 1 多路复用器

用VHDL实现串口 可以实现与pc机的通信 收发 中断都可以 效果比较好-VHDL implement serial port, it can communicate with pc, it can accept and send message, and it can be interrupted.