Altera USB声卡

基于Verilog的FPGA时钟分频程序(FPGA clock frequency division program based on Verilog)

EDA设计实验，用VHDL编写的数字时钟代码，能显示分，秒，小时。根据所设置的频率不同，能够调整时间快慢。-EDA design of experiments, prepared by VHDL code digital clock showing the hours, seconds, hours. According to the frequency of different settings, time to adjust speed.

基于FPGA实现的一种新型数字锁相环-FPGA-based realization of a new type of digital phase-locked loop

verilog ADPLL file with testbench

说明：  FPGA应用状态机版，适合初学者学习状态机三段式，ASMD图的理解和翻译，以及Verilog语言的应用 最后对仿真的一些理解 其中包含HDL设计及testbench描述 根据要求设计了一个能求出一个32bit字中两个相邻0之间最大间隙的电路。(FPGA application state machine version, suitable for beginners to learn state machine three-stage, ASMD chart understanding and translation, and Verilog language application. Finally, some understanding of simulation, including HDL design and testbench description According to the requirements, a circuit is designed to find the maximum gap between two adjacent zeros in a 32 bit word.)

基于VHDL编写的10进制显示输出，基于16进制的10进制控制，适合初学者(VHDL-based display output written in decimal, hexadecimal, 10 hexadecimal-based control, suitable for beginners)

Xilinx FPGA中FFT IP核的使用笔记，内部有FFT硬核的端口说明和具体设置以及源代码，对于数字信号处理研究人员，能图像处理、雷达成像、实时通信开发人员较多的开发时间！(Xilinx FPGA in the FFT IP core using a laptop internal hard core of the FFT port description and specific settings as well as the source code for digital signal processing, image processing, radar imaging, real-time communications developers more development time!)

空调温控电路有限状态自动机， 有ＴＥＭＰ＿ＨＩＧＨ和ＴＥＭＰ＿ＬＯＷ 分别与传感器相连用语检测室内温度．-air-conditioning temperature control circuit finite state automaton, and TEMP_LOW TEMP_HIGH with sensors connected to the indoor temperature detection terminology.

JPEG标准下图象压缩的vhdl实现工程，文件包括一个图像。-JPEG image compression standard works of VHDL realize that the document includes an image.

本工程使用A7系列FPGA产生DDS，用DAC0832进行正弦电压输出(In this project, A7 series FPGA is used to generate DDS, and DAC0832 is used for sinusoidal voltage output)