Altera USB声卡

Computer Arithmetic (press 2000)

八位并行数据转换为串行数据依时钟信号串行输出(Eight bit parallel data to serial data)

Vhdl code for aarithmetic logic unit

rc6 algorithm designed based on verilog and is verified

说明：  对于一串二进制数前置零的计数的Verilog程序(For a string of binary zero count Verilog pre-procedure)

说明：  华为经典设计全套入门技巧，面试经验，设计技巧(Huawei Classic Design Complete Introduction Skills, Interview Experience, Design Skills)

Simulation and Synthesis Techniques for Asynchronous FIFO Design

在FPGA平台实现SPI传输协议开发，SPI为三总线式。(Implementation of SPI transmission protocol development on FPGA platform)

售货机-VHDL语言-已调试通过 真的很好用哦~适合一切学习EDA的初学者，能够让你轻松度过EDA课！~(Vending machine-VHDL language- has been really good with debugging by Oh ~ EDA for all beginners to learn, to let you easily through the EDA class! ~)

RISC CPU IP CORE 可以用于直接的工程开发应用 有详细的说明书-RISC CPU IP CORE can be used to direct the development and application of the project has a detailed brochure