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ed2_prac5_conta_finfin
program in hdl that this open mind in digital resources
- 2009-06-27 08:08:08下载
- 积分：1
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UC3842
基于uc3842的反激电路的saber仿真模型，可调制，波形结果完美(The saber of the flyback circuit simulation model based on uc3842, modulation, waveform perfect results)
- 2015-05-06 21:52:14下载
- 积分：1
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适用于FPGA的SOPC方面的元器件添加，如COMPNENT
适用于FPGA的SOPC方面的元器件添加，如COMPNENT-Applicable to FPGA-SOPC area to add components, such as COMPNENT
- 2022-09-20 17:30:03下载
- 积分：1
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APB 总线
APB 总线。可以实现单个数据在总机与从机之间的读写功能(This can achieve the read and write functions of a single data between the master and the slave .)
- 2017-08-22 16:04:06下载
- 积分：1
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sp605_BRD_rdf0033_13.2_c
spartan605评估板测试代码。xilinx官方资料(spartan605 uation board test code)
- 2014-12-23 22:27:45下载
- 积分：1
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基于VHDL语言的循环码编码器的程序，以一个（15，6）循环码为例...
基于VHDL语言的循环码编码器的程序，以一个（15，6）循环码为例-VHDL language based on the cycle of the program code encoder to a (15,6) cyclic code as an example
- 2022-03-13 14:13:18下载
- 积分：1
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手把手教你学FPGA 仿真篇
手把手教你学FPGA 仿真篇,简单实用。(Hand in hand teach you to learn FPGA simulation, simple and practical.)
- 2018-07-09 21:25:09下载
- 积分：1
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SRAM 简单测试
SRAM简单测试，测试其性能及其速度，判断SRAM是否可用(Test its performance and speed to determine if SRAM is available)
- 2020-07-10 09:58:55下载
- 积分：1
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lut_multiplier
使用verliog设计实现LUT查找表乘法器，通过modelsim仿真验证通过(Designed and implemented using the LUT lookup table verliog multipliers, through simulation by modelsim)
- 2021-04-09 10:18:59下载
- 积分：1
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the program have designed a PCM signal timing modules, including the CLK input,...
该程序设计了一个产生PCM码流时序信号的模块，他包括输入端CLK，SET及输出端Q1,Q2,Q3-the program have designed a PCM signal timing modules, including the CLK input, and output SET Q1, Q2 and Q3
- 2022-02-15 04:03:30下载
- 积分：1
