LPC总线从设备的verilog设计,包含状态机和中断功能。

一段很好地讲述PWM的VHDL硬件代码，可以在不同SOPC上运行实现

10G高速以太网mac VERILOG源码 可仿真可实现(10G high speed Ethernet MAC verilog code can be used for synthesis or inplementation)

Verilog HDL语言编写异步FIFO(Verilog HDL language, asynchronous FIFO)

基于VHDL语言的基带线路码产生电路设计（毕业论文），内涵完整的源代码(Based on VHDL language baseband line code generation circuit design (Thesis), meaning the complete source code)

华为内部资料，包括verilog电路设计，硬件工程师手册，verilog约束，synplify使用指南等。内容较全面。(Huawei internal information, including verilog circuit design, hardware engineers manual, verilog constraints, synplify use guides. Content more comprehensive.)

基于fpga的多功能数字时钟的实现，已经编译过了，绝对可行-fpga-baseed clock

在ＦＰＧＡ中产生的频率可调的锯齿波型信号发生器(The frequency of the FPGA to generate the sawtooth waveform signal generator adjustable)

2. You may use this core in any way, be it academic, commercial, or -- military. Modified or not.-2. You may use this core in any way, be it academic, commercial, or-- military. Modified or not.

VHDL数字系统设计和工程实践2，包含原理，真值表和原理图，以及VHDL源代码.-VHDL digital system design and engineering practice, one that contains principles, truth table and schematic, as well as VHDL source code.

VGA的IP核，下载即可用，解压到指定目录下就可以了，参照里面的read me.-VGA