Implement the 7 segment diplay on spartan 3

基于FPGA的i2s接口输入模块设计，其中有原理图和verilog源码，可在Quartus环境下进行仿真(FPGA-based i2s interface input module design, including schematics and verilog source code, can be simulated in Quartus environment)

组合电路的设计8位加法器设计(ADD8.vhd)-Combinational Circuit Design 8-bit adder design (ADD8.vhd)

基于FPGA的数字低通滤波器 。。。。。(FPGA-based digital low-pass filter。。。。。)

verilog file , FPGA controll vga display- verilog file , FPGA controll vga display

出租车自动计费系统的verilog程序代码(Taxi automated billing system verilog code)

CPLD例程(语言)《Verilog HDL数字控制系统设计实例》AVR_Core.tar.gz-.rar(CPLDprogram dialogue /Verilog language design examples)

基于QuartusII环境下的地铁自动售票系统(Subway auto ticketing system based on QuartusII)

PID算法控制点击速度，PWM脉宽调制方法(PID algorithm to control the motor Speed)

一些简单的Verilog代码，小例程，比如求平均值、七段数码管等等(Some simple Verilog code, small routines, such as averaging, seven digital tubes and so on)

说明：  实现对LCD1602的Verilog HDL编程(the program for LCD1602 based on Verilog HDL)