Implement the 7 segment diplay on spartan 3

中文版DLX流水线技术相关方面介绍以及简单应用 适用于面对初学者讲解(Chinese version of the DLX pipeline technology-related aspects of introduction and a simple application Suitable for beginners to explain face)

SoC-Wishbone System IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。(SoC-Wishbone System IP core VHDL language source code, the need for the development environment is QUARTUS II 6.0.)

本程序使用vhdl编写的jtag接口实现程序,其中有些功能未能实现,希望有人能够帮忙完善!-vhdl the procedures used to prepare the jtag interface procedures, which some of them did not materialize, hope someone can help perfect!

最大最小值寻找程序，可以实现自动查找最大值与最小值(min_max_finder)

adc0809的fpga时序电路接口程序-Sequential Circuits adc0809 the FPGA interface program

verilog实现rtc文档，可用于实现RTC。(verilog realize rtc document can be used to implement the RTC.)

SRAM 读写实验，SRAM存储器的读写操作，Verilog源码有助于提高代码coding能力。使用例程。(SRAM write and read)

本程序包含：EEPROM的功能模型(eeprom.v)、读/写EEPROM的verilog HDL 行为模块（eeprom_wr.v）、信号产生模块（signal.v）和顶层模块(top.v) ，这样可以有一个完整的EEPROM的控制模块和测试文件，本文件通过测试。(This procedure includes: EEPROM of the functional model (eeprom.v), read/write EEPROM acts of verilog HDL modules (eeprom_wr.v), signal generator module (signal.v) and top-level module (top.v), this can have a EEPROM complete control module and test document, this document is to pass the test.)

利用LMP的20bit counter,比自带的cout进位要快的多。已经同错综合和时序仿真。-LMP

步进电机位置系统 步进电机位置系统block symbol file 步进电机位置系统的Verilog HDL程序设计 已编译通过-Stepper motor stepper motor position location system system block symbol file location stepper motor system Verilog HDL program design has been compiled through