Implement the 7 segment diplay on spartan 3

用VERILOG编写的数字电子钟，用数码管进行显示时间-VERILOG prepared with digital electronic clock with a nixie tube display time

自己写的pwm占空比采集与输出 但是没有计算占空比，如果又需要可以自己修改计算并显示占空比，该程序已经测试过了，可以使用，拿出来供大家分享，新手写的如有不足请大牛带飞。

这是用verilog语言实现的1024点ff程序t-This is achieved using Verilog 1024 language ff procedures point t

六十进制计数器用于计数等操作，代码的实现方式很简单(Six decimal counter for counting operation, the code is very simple implementations)

说明：  Browser modularization processing, browser modularization combing, browser modularization expansion

详细讲解时序约束培训教材，有利于更好对时序约束的理解(Timing constraints elaborate training materials, facilitate better understanding of the timing constraints)

说明：  在MATLAB下自编实现快速傅里叶分析，(Fast fft own procedures, faster than the system call fft slowe)

Qutuas II v7.1的key_gen 对sp1无效 这就是个v7.1 sp1的key_gen -Key_gen the Qutuas II v7.1 for sp1 invalid This is the v7.1 sp1 months key_gen

SRIO接口物理层的实现代码，非常复杂，完全自己用verilog编写，支持5G速率，可以作为开发参考(SRIO interface implementation code, the physical is very complex, completely written in verilog, support rate of 5 g, will be helpful to the development)

数字频率计 数字频率计-Digital frequency meter digital frequency meter