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netlist
vhdl program of matlab file converted to vhdl
- 2015-02-06 21:21:13下载
- 积分:1
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DWT-VHDL
小波变换的VHDL代码,内带正变换逆变换的测试文件。(Wavelet transform VHDL code, with a positive transformation within the inverse transform of the test file.)
- 2010-05-14 20:37:27下载
- 积分:1
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ADC实验
用于单片机的adc采集实验,经过降噪处理,结果精确(ADC acquisition experiment for single chip computer, after noise reduction processing, the result is accurate)
- 2018-11-27 21:41:13下载
- 积分:1
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Arty-Z7-20-hdmi-out-master
说明: Arty Z7 20 HDMI output
- 2021-04-24 15:18:47下载
- 积分:1
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VHDL_COUNTING 与 4 使脉冲和使用 3 按钮了,下来,停止 (Mạch đếm với 4 xung ENA sử dụng 3 nút nhấn lên,xuống và dừng l
VHDL_COUNTING 与 4 使脉冲和使用 3 按钮了,下来,停止 (Mạch đếm với 4 xung ENA sử dụng 3 nút nhấn lên,xuống và dừng lại)
- 2022-03-19 05:46:27下载
- 积分:1
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fffffff
如上图所示, Rst是低电平有效的系统复位信号,Clk是时钟信号。AB[5:0]是地址信号,DB[7:0]是数据信号,wr是低电平有效的写信号。start是启动信号。
模块中有一个64x8的双端口的存储器。系统复位结束后,可以通过AB、DB和wr信号向同步存储器写入数据。当写入64个数据后,给出一个Clk周期宽度的脉冲信号start,则系统从存储器0地址处开始读出数据,读出的8位数据从低位开始以3位为一组,每个时钟周期输出一组,即第一个时钟周期输出[2:0]位,第二个时钟周期输出[5:3]位,第三个周期输出1地址的[0]位和0地址的[7:6]位,直至将存储器中64x8数据全部输出。若最后一组不足三位,则高位补0。
(As shown above, Rst is an active-low system reset signal, Clk is a clock signal. AB [5: 0] is the address signal, DB [7: 0] is the data signal, wr write signal is active low. start is the start signal. Module in a dual port memory of 64x8. After the reset, you can write data to the synchronous memory by AB, DB and wr signals. When data is written to 64, given the width of a pulse signal Clk cycle start, the system begins to read the memory address 0, 8 data read out a low starting with three as a group, each clock outputs a set period, which is the first clock cycle of the output [2: 0] bits, the second clock cycle output [5: 3] position, the third cycle of the output of an address [0] and 0 address [7 : 6] bit, until all the data in memory 64x8 output. If the last group of less than three, the high 0s.)
- 2020-11-04 20:39:51下载
- 积分:1
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LS-versus-MMSE
这是基于MIMO-OFDM的同步算法研究的源程序。本程序采用的极大似然估计的方法。(This is based on MIMO-OFDM synchronization algorithm source code. The program uses the method of maximum likelihood estimates.
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- 2012-12-13 15:32:49下载
- 积分:1
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8位7段LED显示源码,扫描显示,稳定高效
8位7段LED显示源码,扫描显示,稳定高效-seven of the eight LED source, scanning, stable and efficient
- 2022-02-15 21:05:29下载
- 积分:1
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DDs直接数字频率合成器的源代码,其中包括采用IP核和普通两种方式...
DDs直接数字频率合成器的源代码,其中包括采用IP核和普通两种方式-DDS Direct Digital Synthesizer source code, including the use of IP core and the general two ways
- 2022-01-23 11:02:21下载
- 积分:1
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disptest
模拟示波器的现实程序,有x,y和光标。采用AD5440输出,现实效果很好。(示波器x-y方式)(Analog oscilloscope reality program, there are x, y and cursor. Using AD5440 output, real good results. (Xy oscilloscope mode))
- 2013-09-13 23:18:19下载
- 积分:1