50 cases of practical CPLD design, very classic CPLD design, including 50 typica...

6通道正弦波发生器，产生频率，相位，幅值都可调的正弦波形-6-channel sine wave generator, resulting in frequency, phase, amplitude of the sinusoidal waveform are adjustable

matlab code for communication

加法器，输入两个整数，用电路图形式将其逻辑原理呈现出来，该加法器为8位运算，每一位都对应一张电路图，可展示其完整过程(Adder, input two integer, with circuit diagram form its logical principle appear, this adder is 8 bit arithmetic, each corresponding to a circuit diagram, can show the complete process)

ISE 9.2 serials working

基于FPGA的UDP网络图像传输实验，FPGA完成了MT9V034的RAW图像采集缓存，NIOS完成了图像的UDP封包，DM9000芯片完成了MAC和PHY的功能。(Based on the UDP FPGA network image transmission experiment, FPGA completed the RAW MT9V034 image acquisition cache, NIOS completed the image of the UDP packets, DM9000 chip MAC and PHY completed the function.)

实现基于FPGA的vga显示，亲测能编译得过，不同开发版应该要相应改动（PS: 不太了解）

16： 00 FFT VHDL源代码，xFFT16快速傅立叶变换（FFT）核心计算16点复数FFT。输入数据是16个复数值的向量，表示为16位2s补码-16位表示一个数据的实部和虚部。

vhdl编写的fifo程序-VHDL procedures prepared by the fifo

System Verilog for design verification

说明：  verilog语言编写的简单FPGA 的从机模式 spi 通讯(Slave mode SPI communication of FPGA)