电子表，实现计时记分计秒的功能，同时可以对时分秒进行校正，实现调时功能。...

fpga里实现 uart 经典 vhdl语言写的 ise工程文件-fpga implementation in vhdl language classic uart of ise project file

这是用verilogHDL写的m序列发生器，简单易用，代码非常易读(It is written verilogHDL m sequence generator, easy to use, the code is very easy to read)

说明：  为串口收发器以及汉明编码，将电脑通过串口发送的7位数据转化成汉明码显示于led上，或把接收到的11位汉明码解码并验错纠错(For the serial port transceiver, and Hamming codes, the computer through the serial port into 7-bit data displayed on the led on the Hamming code, or to receive the 11 Hamming code error correction decoding and experience)

广东工业大学硕士论文《SVPWM算法优化及其FPGA/CPLD实现》，在详细分析经典SVPWM算法基础上，提出一种优化算法，并在FPGA上实现。论文附录包含VHDL源码。(Guangdong University Thesis " SVPWM algorithm to optimize its FPGA/CPLD realization" in the detailed analysis of the classical SVPWM algorithm is proposed based on an optimization algorithm, and implemented on FPGA. Paper appendix contains VHDL source code.)

本章介绍了两个EDA技术的综合应用设计实例:数字闹钟和直接数字频率合成器DDS。-EDA chapter describes the two technologies integrated application design example: digital alarm clock and direct digital synthesizer DDS.

说明：  模糊控制器verilog程序，模糊控制器最简单的实现方法是将一系列模糊控制规则离线转化为一个查询表（又称为控制表）。这种模糊控制其结构简单，使用方便，是最基本的一种形式。(Verilog program of fuzzy controller)

用VHDL编写的步进电机控制方法.供大家参考用.-prepared using VHDL stepper motor control methods. For your reference.

说明：  FPGA 读写 SRAM 存储块，verilog代码(Read and write SRAM memory block and Verilog code in FPGA)

一个八位的并行输入，串行输出的编码器；带有开头结尾帧。(It is an encode with eight palallel input and a serial output.)