电子表，实现计时记分计秒的功能，同时可以对时分秒进行校正，实现调时功能。...

verilog的入门级别的例子（转载）-Verilog entry-level examples (reproduced)

The VHDL Cookbook First Edition July, 1990 Peter J. Ashenden Dept. Computer Science University of Adelaide South Australia

Xilinx FPGA reset usage

注意：是verilog语言写的 一bit的全加器，实现4位数的串行加法器，一个时钟能完成一次一bit的全加(Note: It is verilog language to write a bit full adder, to achieve four-digit serial adder, a clock can be completed once a bit full adder)

说明：  4位加法器，4位数字相加及进位功能的实现，主要利用Verilog语言实现，简单轻松，且代码量少(a adder which can realize 4 bit numbers adding)

Lab view using FPGA traing on lcd pannel

Z源逆变器简单升压模拟仿真。调制方式为SPWM，通过设置三角波幅值和比较电压，即可调节输出电压。(Z-source inverter simple step-up simulation. Modulation mode SPWM, by setting the the triangle amplitude and the comparison voltage to regulate the output voltage.)

这是VHDL中计数器的代码。

the basic system of nexys3(soft core)

Verilog 最大公约数设计RTL级代码和芯片设计图(Verilog GCD Design and synthesis layout )